llvm dev - Mar 2016 - infer correct types from the pattern

i'm getting a

Could not infer all types in pattern!

error in my backend. it is happening on the following instruction:

VGETITEM:  (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32}
VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)).

how do i make it use appropriate types? in other words if it is f32 then
use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start?

any help is appreciated.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20160330/e8cef85b/attachment.html>

On 3/30/2016 4:42 PM, Rail Shafigulin via llvm-dev
wrote:
> i'm getting a
>
> Could not infer all types in pattern!
>
> error in my backend. it is happening on the following instruction:
>
> VGETITEM:  (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32}
> VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)).
>
> how do i make it use appropriate types? in other words if it is f32 then
> use v4v32 and if it is i32 then use v4f32. i'm not sure even where to
start?
You can use a cast, and force one type in the pattern, then use the 
other one in a Pat:

def VGETITEM:
   [(set GPR:$rD, (extractelt (v4i32 VR:$rA), GPR:$rB))]

def: Pat<(extractelt (v4f32 VR:$rA), GPR:$rB)),
          (VGETITEM VR:$rA, GPR:$rB)>;

-Krzysztof


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

>
> You can use a cast, and force one type in the pattern, then use the other
> one in a Pat:
>
> def VGETITEM:
>   [(set GPR:$rD, (extractelt (v4i32 VR:$rA), GPR:$rB))]
>
> def: Pat<(extractelt (v4f32 VR:$rA), GPR:$rB)),
>          (VGETITEM VR:$rA, GPR:$rB)>;
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
Krzysztof,

I'm curious how do you know LLVM so well? Most of the times your answers
are exactly what I need. I was recommended to read code (as usual), however
it is challenging without knowing what the code is trying to express. IMHO
it is better to have a concept first and then express it in code. I've been
trying to find books, tutorials, etc, but there doesn't seem to be good
examples out there. Basically my questions are:

1. What is your adivce on learning LLVM (and compiler design)?
2. Is there a way to do quickly and efficiently or I will just have to
suffer through several years of painstaking trial and error as well as my
own research on the topic?

Any help is appreciated.


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20160331/a3ac410c/attachment.html>

>
> def VGETITEM:
>   [(set GPR:$rD, (extractelt (v4i32 VR:$rA), GPR:$rB))]
>
> def: Pat<(extractelt (v4f32 VR:$rA), GPR:$rB)),
>          (VGETITEM VR:$rA, GPR:$rB)>;
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
What about load instruction? I tried the same approach but I got an error.

error: In anonymous_570: Type inference contradiction found, merging
'{v4i32:v4f32}' into '{i32:f32}'

For some reason I had no issues doing the same for store.

Any help is really appreciated.

Here is what I tried for load:

// Addressing modes.
def ADDRri : ComplexPattern<i32, 2, "SelectAddr", [frameindex],
[]>;

// Address operands
def MEMri : Operand<i32> {
  let PrintMethod = "printMemOperand";
  let EncoderMethod = "getMemoryOpValue";
  let DecoderMethod = "DecodeMemoryValue";
  let MIOperandInfo = (ops GPR, i32imm);
}

class LOAD<bits<4> subop, string asmstring, list<dag> pattern>
  : InstLD<subop, (outs GPR:$rD), (ins MEMri:$src),
           !strconcat(asmstring, "\t$rD, $src"), pattern> {
  bits<5> rD;
  bits<21> src;

  let Inst{25-21} = rD;
  let Inst{20-0} = src;
}

class LOADi32<bits<4> subop, string asmstring, PatFrag opNode>
  : LOAD<subop, asmstring, [(set (i32 GPR:$rD), (opNode ADDRri:$src))]>;

let mayLoad = 1 in {
  let Itinerary = l_lwz in
    def LWZ : LOADi32<0x1, "l.lwz", load>;
}

class VLOADi32<bits<4> subop, string asmstring, PatFrag opNode>
  : VLOAD<subop, asmstring, [(set (v4i32 VR:$rD), (opNode ADDRri:$src))]>;

let mayLoad = 1 in {
  let Itinerary = v_lwz in
    def VLWZ : VLOADi32<0x2, "v.lwz", load>;
}

// Cast load of a floating point vector to use the same
// operation as a load of an integer vector.
def: Pat<(set (v4f32 VR:$rD), (load ADDRri:$src)),
         (VLWZ VR:$rD, ADDRri:$src)>;



-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20160404/b5a91125/attachment.html>