search for: extractelt

Displaying 20 results from an estimated 25 matches for "extractelt".

2020 Jan 10
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...operations. Now that it appears that this would be useful to do on yet another operation, I'm wondering what people think about doing this in the target-independent DAG Combiner for any legal/custom operation on the target. TL; DR; The generic pattern would look like this: (build_vector (op (extractelt %a, 0), [(extractelt %b, 0)]...), (op (extractelt %a, 1), [(extractelt %b, 1)]...), ...) Basically, if the build vector is built from the same operation applied on elements extracted from another vector (or pair of vectors for binary ops), then we can check for the legality of the op...
2019 Nov 28
2
Question on pattern matching extractelt
Hi, I have an issue with pattern matching. I have the following SelectionDAG: t13: i32 = extract_vector_elt t2, Constant:i64<1> That I am trying to match with the following pattern: def : Pat<(extractelt (v4i16 SingleReg:$v), 1), (SRADd1 SingleReg :$v, (i64 16))>; But for some reason the pattern does not match. It seems to be due to the fact extract_vector_elt's result type is i32 (because i16 is not a legal type on our processor), but according to the comment in ISDOpcodes.h, it is allow...
2011 Dec 10
5
[LLVMdev] Types inference in tblgen: Multiple exceptions
...From clang, I emulate a complex multiplication using vectors and, at >> the IR, I got this tblgen-friendly pattern (real component) : >> >> (set RARegs:$dst, (insertelt RARegs:$src, >> (i16 (trunc (add >> (ncmul >> (sext (i16 (extractelt RARegs:$a, imm))), >> (sext (i16 (extractelt RARegs:$b, imm))) >> ), >> (ncmul >> (sext (i16 (extractelt RARegs:$a, imm))), >> (sext (i16 (extractelt RARegs:$b, imm))) >> ) >>...
2011 Dec 09
2
[LLVMdev] Types inference in tblgen: Multiple exceptions
...unctional units to perform complex multiplications. From clang, I emulate a complex multiplication using vectors and, at the IR, I got this tblgen-friendly pattern (real component) : (set RARegs:$dst, (insertelt RARegs:$src, (i16 (trunc (add (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARegs:$b, imm))) ), (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARegs:$b, imm))) ) ))), imm) ) where RARegs is a register class...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...%mul, <i128 64, i128 64> %trunc = trunc <2 x i128> %shift to <2 x i64> ret <2 x i64> %trunc } On PPC, the legalizer will scalarize this since we do not have v2i128. Then the DAG combiner will produce the pattern I am referring to in this RFC: (v2i64 build_vector (mulhs (extractelt %a, 0), (extractelt %b, 0)), (mulhs (extractelt %a, 1), (extractelt %b, 1))) And if the target has mulhs legal for the vector type, this is strictly worse. So no matter what we do in InstCombine or the SLP vectorizer, we will end up with non-optimal code. If we also handle shu...
2011 Dec 09
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...plex multiplications. >  From clang, I emulate a complex multiplication using vectors and, at > the IR, I got this tblgen-friendly pattern (real component) : > > (set RARegs:$dst, (insertelt RARegs:$src, >           (i16 (trunc (add >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >             (sext (i16 (extractelt RARegs:$b, imm))) >             ), >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >             (sext (i16 (extractelt RARegs:$b, imm))) >            ) >            ))), >           imm) ) &...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...t; %shift to <2 x i64> >> ret <2 x i64> %trunc >> } >> On PPC, the legalizer will scalarize this since we do not have v2i128. >> Then the DAG combiner will produce the pattern I am referring to in this >> RFC: >> >> (v2i64 build_vector (mulhs (extractelt %a, 0), (extractelt %b, 0)), >> (mulhs (extractelt %a, 1), (extractelt %b, 1))) >> >> And if the target has mulhs legal for the vector type, this is strictly >> worse. So no matter what we do in InstCombine or the SLP vectorizer, we >> will end up w...
2011 Dec 10
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>> (i16 (trunc (add >>> (ncmul >>> (sext (i16 (extractelt RARegs:$a, imm))), >>> (sext (i16 (extractelt RARegs:$b, imm))) >>> ), >>> (ncmul >>> (sext (i16 (extractelt RARegs:$a, imm))), >>> (sext (i16 (extractelt RARegs:$b, imm))) >>>...
2014 Aug 11
2
[LLVMdev] tablegen pattern
...sic function( say " float:$dst llvm.irmod( vec4:$src)" which takes a vec4, output a float. I think the procedure is: when I see the intrinsic llvm.irmod, I need to call "extractlt( mod($src), 0)”, So I tried to define a pattern “ def Pat<( i32 ( llvm.irmod vf432:$src)), (extractelt( mod v4f32:$src ), 0)>”, but it reports ERROR” Cannot use “extractelt” in an output pattern”. I knew I can easily do it via lowering operation by separating the “extractelt” node out. But can I do it via tablgen? Best kevin -------------- next part -------------- An HTML attachment was s...
2011 Dec 10
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...e a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>>           (i16 (trunc (add >>>            (ncmul >>>             (sext (i16 (extractelt RARegs:$a, imm))), >>>             (sext (i16 (extractelt RARegs:$b, imm))) >>>             ), >>>            (ncmul >>>             (sext (i16 (extractelt RARegs:$a, imm))), >>>             (sext (i16 (extractelt RARegs:$b, imm))) >>>          ...
2011 Dec 10
1
[LLVMdev] Types inference in tblgen: Multiple exceptions
...using vectors and, at >>>> the IR, I got this tblgen-friendly pattern (real component) : >>>> >>>> (set RARegs:$dst, (insertelt RARegs:$src, >>>> (i16 (trunc (add >>>> (ncmul >>>> (sext (i16 (extractelt RARegs:$a, imm))), >>>> (sext (i16 (extractelt RARegs:$b, imm))) >>>> ), >>>> (ncmul >>>> (sext (i16 (extractelt RARegs:$a, imm))), >>>> (sext (i16 (extractelt RARegs:$b, imm)...
2016 Mar 30
3
infer correct types from the pattern
i'm getting a Could not infer all types in pattern! error in my backend. it is happening on the following instruction: VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32} VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)). how do i make it use appropriate types? in other words if it is f32 then use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start? any help is appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -----------...
2011 Dec 02
0
[LLVMdev] Error: Type constraint application shouldn't fail!
...l : SDNode<"ISD::MUL" , SDTIntBinOp, [SDNPAssociative]>; def mula_pat : PatFrag<(ops node:$a, node:$b), (add (ncmul (sext (i16 (extractelt node:$a, (i32 0)))), (sext (i16 (extractelt node:$b, (i32 1)))) ), (ncmul (sext (i16 (extractelt node:$a, (i32 1)))), (s...
2016 Aug 18
3
extract_vector_elt type mismatch?
Hi there, I'm trying to map extract_vector_elt use the following pattern in tbl file. Def : Pat <(i64 (extractelt v2i32:$src, 0)), (i64 (SRLIMM GPR:$src, 32))>; But the tblgen shows : Type inference contradiction found , forcing v2i32 to have a vector element of type i64 But the manual says this instruction allows return type to be larger than element type. Anyone can show me any pointers ? Thanks, Xia...
2016 Mar 30
1
infer correct types from the pattern
On 3/30/2016 4:42 PM, Rail Shafigulin via llvm-dev wrote: > i'm getting a > > Could not infer all types in pattern! > > error in my backend. it is happening on the following instruction: > > VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32} > VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)). > > how do i make it use appropriate types? in other words if it is f32 then > use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start? You can use a cast, and force one type in the pattern, then use the other on...
2009 Dec 02
1
[LLVMdev] More AVX Advice Needed
...trinsic. > X86ISD::INSERTPS is an extra instruction for ISel; it's used inside > the custom lowering for INSERT_VECTOR_ELT and VECTOR_SHUFFLE. Yes, that's how I found out about it. :) Why not just use ISD::INSERT_VECTOR_ELT? And what's the difference between vector_extract and extractelt in TargetSelectionDAG.td? Ditto vector_insert vs. insertelt. -Dave
2017 Nov 11
2
RFC: [GlobalISel] Towards a generic MI combiner framework
...rules >> with more than one match root. For example (using SelectionDAG patterns): >> (set $dst1:GPR32, (i32 (load $ptr:GPR64))) >> (set $dst2:GPR32, (i32 (load (add $ptr:GPR64 4)))) >> into: >> (set $tmp:GPR64, (v2s32 (load $ptr:GPR64))) >> (set $dst1, (extractelt $tmp:GPR64, 0)) >> (set $dst2, (extractelt $tmp:GPR64, 1)) >> Or something along those lines (such as fusing div/mod together). The >> combiner should be smart enough to make the root the $ptr, and follow >> the use of $ptr into the load/add, then follow the def to the 4...
2017 Nov 12
0
RFC: [GlobalISel] Towards a generic MI combiner framework
...more than one match root. For example (using SelectionDAG patterns): >>> (set $dst1:GPR32, (i32 (load $ptr:GPR64))) >>> (set $dst2:GPR32, (i32 (load (add $ptr:GPR64 4)))) >>> into: >>> (set $tmp:GPR64, (v2s32 (load $ptr:GPR64))) >>> (set $dst1, (extractelt $tmp:GPR64, 0)) >>> (set $dst2, (extractelt $tmp:GPR64, 1)) >>> Or something along those lines (such as fusing div/mod together). The combiner should be smart enough to make the root the $ptr, and follow the use of $ptr into the load/add, then follow the def to the 4. >> T...
2012 Jan 14
0
[LLVMdev] Vector ops out of loops
...%cmp, label %for.body, label %for.end for.end: ; preds = %for.body store i32 50, i32* @i, align 4 store <2 x i16> %6, <2 x i16>* @c, align 4 ret void } The store to "c" is efficiently moved out of the loop but insertelt and extractelt are not. Because we are always accessing the second element of vector c, is it not more efficient to move extractelt to the loop entry and insertelt to the end ? Ivan
2017 Nov 10
2
RFC: [GlobalISel] Towards a generic MI combiner framework
> On Nov 10, 2017, at 10:19 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/10/2017 11:12 AM, Amara Emerson via llvm-dev wrote: >> Hi everyone, >> >> This RFC concerns the design and architecture of a generic machine instruction combiner/optimizer framework to be developed as part of the GISel pipeline. As we transition from