> On Jul 31, 2015, at 10:49 AM, Steve King <steve at metrokings.com>
wrote:
>
> Hello LLVM,
> If there are any, can someone please explain rules of thumb for when
> to do a PerformDAGCombine operation in ISelLowering vs. when to do a
> DAG to DAG transformation?
>
> I'm specifically thinking of an AND + SRL merge into a bit field
> extract type instruction. I see that the ARM target does this in
> DAG-to-DAG, but this is literally a combine of two instructions,so why
> not DAGCombine?
>
> Thanks,
> -steve
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It’s better to do something as a DAG combine if doing so is more likely to
expose other DAG combine opportunities. For example, in AMDGPU we have to do a
unit conversion to the hardware sin/cos instructions. We could implement this as
an instruction pattern for the sin node with the fmul by a constant conversions
there. However if the unit conversion is done during custom lowering and you
have another fmul input to the sin node, with fast math the 2 fmuls by a
constant will be folded into one.
In the case of bitextract instructions it’s kind of harder to analyze them after
they are created, so might seem less worth it to have those done in the DAG.
However, we currently have at least 3 in-tree targets all trying to match some
variant of pretty much the same instruction, so I would like it if we had a
generic bit extract node and moved all of the pattern matching to DAG combiner.
-Matt
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