search for: srl

Displaying 20 results from an estimated 492 matches for "srl".

Did you mean: sol
2017 Feb 14
3
Samba AD domain member with SSSD: ACL not work
...user without problem. My problem occur when I try from windows to modify some new rights (ACL's) to new folder on samba share. The folder is created correctly but if I add some groups or setup ACL's I get this error log and the new ACL's is not saved: > feb 14 12:07:42 samba-dati.srl.local smbd[1178]: [2017/02/14 12:07:42.149812,  0] ../source3/smbd/posix_acls.c:2080(create_canon_ace_lists) > feb 14 12:07:42 samba-dati.srl.local smbd[1178]:   create_canon_ace_lists: unable to map SID S-1-5-21-347198863-3916504048-2821235790-1213 to uid or gid. This is my testparm -s (smb.co...
2017 Feb 15
3
Samba AD domain member with SSSD: ACL not work
...t; Yes. I use sssd, If this is not a problem for samba. > > > In which case you should remove the 'idmap config' lines from > > smb.conf. > > Ok, now I have remove this 4 lines, restart smb and test: ACLs still > not work. > > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   ***** > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]: > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   Samba name server > SAMBA-DATI is now a local master browser for workgroup SRL on subnet > 192.168.1.5 > > feb 14 17:45:24 samba-dati.srl.loc...
2017 Feb 15
2
Samba AD domain member with SSSD: ACL not work
...ati). If I try to access to it from a windows PC into domain (\\server-dati) do not access and require a user and password If I try to access it via smbclient from samba on another Linux PC (es. my notebook) not in domain I can access only if I specify the domain+user like this: > smbclient -Usrl\\administrator%pwd //server-dati/dati If I do not specify the domain but only user, I do not access and show this error: > smbclient -Uadministrator%pwd //server-dati/dati -d3 > lp_load_ex: refreshing parameters > Initialising global parameters > rlimit_max: increasing rlimit_max (102...
2009 Dec 01
4
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
...Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. // ShAmt >= NVTBits Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); Hi2 = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); return true; case ISD::SRL: // ShAmt < NVTBits Hi1 = DAG.getConstant(0, NVT); // Hi part is zero. Lo1 = DAG.getNode(ISD...
1999 Oct 21
1
left.solve
I have sort of an emergency question for the list. One of my professors for an S-Plus intensive class distributed a function to produce partial regression plots. I need to run it under R, because I'm doing the homework on my home computer with a modem; hence I don't have the speed required to emulate X-Windows and run S Plus off one of the campus servers. Bottom line: I'm using R.
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
...and LowerSTORE() routines (which emit between 1 and O(10) SDValues, depending on alignment information), and then runs DAGCombine. To lower an i16 STORE that is known to be in the high-addressed 2 bytes of a word on my little-endian target, I emit and LD4 from the word-aligned address and an SRL 16 to shift the i16 into the LSbits of the register. DAGCombine visit()s an ISD::SRL node and notices that it is right-shifting the result of an LD4 from %arrayidx4 by 16 bits, and replaces it with an LD2 from %arrayidx+2. Replaces -------- 0x17f7070: i32,ch = load 0x17faa00, 0x17f7f70, 0x17f6a...
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
...ch emit between 1 and O(10) SDValues, >> depending on alignment information), and then runs DAGCombine. To lower >> an i16 STORE that is known to be in the high-addressed 2 bytes of a word >> on my little-endian target, I emit and LD4 from the word-aligned address >> and an SRL 16 to shift the i16 into the LSbits of the register. >> >> DAGCombine visit()s an ISD::SRL node and notices that it is >> right-shifting the result of an LD4 from %arrayidx4 by 16 bits, and >> replaces it with an LD2 from %arrayidx+2. >> >> Replaces >> ----...
2009 Dec 01
0
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a
2017 Feb 14
1
Samba AD domain member with SSSD: ACL not work
...re not using winbind, you are using sssd. Yes. I use sssd, If this is not a problem for samba. > In which case you should remove the 'idmap config' lines from > smb.conf. Ok, now I have remove this 4 lines, restart smb and test: ACLs still not work. > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   ***** > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:    > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   Samba name server SAMBA-DATI is now a local master browser for workgroup SRL on subnet 192.168.1.5 > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:    >...
2018 Jan 19
1
[Possibile SPAM] Re: Problem with Gluster 3.12.4, VM and sharding
...write-behind on and flush-behind on too. Il 18/01/2018 13:30, Krutika Dhananjay ha scritto: > Thanks for that input. Adding Niels since the issue is reproducible > only with libgfapi. > > -Krutika > > On Thu, Jan 18, 2018 at 1:39 PM, Ing. Luca Lazzeroni - Trend Servizi > Srl <luca at gvnet.it <mailto:luca at gvnet.it>> wrote: > > Another update. > > I've setup a replica 3 volume without sharding and tried to > install a VM on a qcow2 volume on that device; however the result > is the same and the vm image has been corru...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...() routines (which emit between 1 and O(10) SDValues, > depending on alignment information), and then runs DAGCombine.  To lower > an i16 STORE that is known to be in the high-addressed 2 bytes of a word > on my little-endian target, I emit and LD4 from the word-aligned address > and an SRL 16 to shift the i16 into the LSbits of the register. > > DAGCombine visit()s an ISD::SRL node and notices that it is > right-shifting the result of an LD4 from %arrayidx4 by 16 bits, and > replaces it with an LD2 from %arrayidx+2. > > Replaces > -------- > 0x17f7070: i32,ch...
2018 Jan 18
1
[Possibile SPAM] Re: Problem with Gluster 3.12.4, VM and sharding
Thanks for that input. Adding Niels since the issue is reproducible only with libgfapi. -Krutika On Thu, Jan 18, 2018 at 1:39 PM, Ing. Luca Lazzeroni - Trend Servizi Srl < luca at gvnet.it> wrote: > Another update. > > I've setup a replica 3 volume without sharding and tried to install a VM > on a qcow2 volume on that device; however the result is the same and the vm > image has been corrupted, exactly at the same point. > > Here'...
2007 Mar 30
1
[LLVMdev] Cleanups in ROTL/ROTR DAG combiner code
...ranches/llvm-spu) (revision 2118) @@ -1488,23 +1488,24 @@ } unsigned OpSizeInBits = MVT::getSizeInBits(VT); + SDOperand LHSShiftArg = LHSShift.getOperand(0); + SDOperand LHSShiftAmt = LHSShift.getOperand(1); + SDOperand RHSShiftAmt = RHSShift.getOperand(1); // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) - if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && - RHSShift.getOperand(1).getOpcode() == ISD::Constant) { - uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->ge...
2002 Feb 01
4
error in rsync protocol data stream (code 12) at token.c(288)
...ng: rsync version 2.5.2 protocol version 26 Copyright (C) 1996-2002 by Andrew Tridgell and others <http://rsync.samba.org/> Capabilities: 64-bit files, socketpairs, hard links, symlinks, batchfiles, no IPv6, 64-bit system inums, 64-bit internal inums -- Stuart Anderson sba@srl.caltech.edu http://www.srl.caltech.edu/personnel/sba
2018 Jan 18
1
[Possibile SPAM] Re: Problem with Gluster 3.12.4, VM and sharding
...ger-lock: enable network.remote-dio: enable performance.low-prio-threads: 32 performance.io-cache: off performance.read-ahead: off performance.quick-read: off transport.address-family: inet nfs.disable: on performance.client-io-threads: off Il 17/01/2018 14:51, Ing. Luca Lazzeroni - Trend Servizi Srl ha scritto: > > Hi, > > after our IRC chat I've rebuilt a virtual machine with FUSE based > virtual disk. Everything worked flawlessly. > > Now I'm sending you the output of the requested getfattr command on > the disk image: > > # file: TestFUSE-vda.qcow2 &g...
2017 Feb 15
0
Samba AD domain member with SSSD: ACL not work
...amba. > > > > > In which case you should remove the 'idmap config' lines from > > > smb.conf. > > > > Ok, now I have remove this 4 lines, restart smb and test: ACLs > > still > > not work. > > > > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   ***** > > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]: > > > feb 14 17:45:24 samba-dati.srl.local nmbd[3338]:   Samba name > > > server > > > > SAMBA-DATI is now a local master browser for workgroup SRL on > > subnet > >...
2018 Jan 17
1
[Possibile SPAM] Re: Problem with Gluster 3.12.4, VM and sharding
...632d3966623765306232336263652f54657374465553452d7664612e71636f7732 trusted.glusterfs.shard.block-size=0x0000000004000000 trusted.glusterfs.shard.file-size=0x00000000c15300000000000000000000000000000060be900000000000000000 Hope this helps. Il 17/01/2018 11:37, Ing. Luca Lazzeroni - Trend Servizi Srl ha scritto: > > I actually use FUSE and it works. If i try to use "libgfapi" direct > interface to gluster in qemu-kvm, the problem appears. > > > > Il 17/01/2018 11:35, Krutika Dhananjay ha scritto: >> Really? Then which protocol exactly do you see this issue...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...1 and O(10) SDValues, >>> depending on alignment information), and then runs DAGCombine.  To lower >>> an i16 STORE that is known to be in the high-addressed 2 bytes of a word >>> on my little-endian target, I emit and LD4 from the word-aligned address >>> and an SRL 16 to shift the i16 into the LSbits of the register. >>> >>> DAGCombine visit()s an ISD::SRL node and notices that it is >>> right-shifting the result of an LD4 from %arrayidx4 by 16 bits, and >>> replaces it with an LD2 from %arrayidx+2. >>> >>&gt...
2015 Aug 19
3
[RFC] Improving integer divide optimization (related to D12082)
Hello LLVM, A recent commit creates the isIntDivCheap() target query. http://reviews.llvm.org/D12082 The current approach has a couple shortcomings. First, when targets decide divide is cheap, the DAGCombiner ignores obvious power-of-2 optimizations. In the targets I know, shifts are cheaper than divides in both speed and size. The target cannot see the value in the isIntDivCheap() call, so
2019 Jun 10
2
Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL
LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3") However, setting setO...