search for: bitextract

...wering.cpp setOperationAction(ISD::LOAD, MVT::i64, Custom); Transform load i64 to load v2i32 during type legalization. During op legalization, load v2i32 is found unaligned (4 v.s. 8), so stack load/store instructions are generated. This is one problem. Besides of that, our target has bitset/bitextract instructions, we want to use them on bitfield access, too. But don't know how to do that. Thanks. Regards, chenwj 2017-06-15 0:10 GMT+08:00 mats petersson <mats at planetcatfish.com>: > Would probably help if you explained which backend you are working on > (assuming it's a...

Hello LLVM, If there are any, can someone please explain rules of thumb for when to do a PerformDAGCombine operation in ISelLowering vs. when to do a DAG to DAG transformation? I'm specifically thinking of an AND + SRL merge into a bit field extract type instruction. I see that the ARM target does this in DAG-to-DAG, but this is literally a combine of two instructions,so why not DAGCombine?

Hi All, Is there known issue that LLVM is bad at codegen for some language structure, say C bitfield? Our custom backend generates inefficient code for bitfield access, so I am wondering where should I look into first. Thanks. Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed...