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Matt Arsenault

2014-Jul-09 19:51 UTC

[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

On 07/09/2014 12:41 PM, Matt Arsenault wrote:> On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote:
>>     Thank you Kevin!!!
>>     If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, 
>> "fptrunc  double %tmp to float" is right, but "fptrunc
float %tmp to
>> half" is wrong). My target platform is MIPS.  The command as
following:
>>
>> NEON:
>> vcvtt.f16.f32 s2, s0
>>
>> llvm Code:
>>
>> %Vt_2 = load float* %VFP_s0, align 4
>> %Vt3_1 = fptrunc float %Vt_2 to half
>> %Vt4_1 = bitcast half %Vt3_1 to i16
>> %Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>*
>> %Vrti_1 = load <2 x i16>* %Vt2_2, align 4
>> %Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1
>> %Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>*
>> store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4
>>
>> Error Log:
>> LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 
>> 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to 
>> f16> [ID=52]
>> 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 
>> 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
>> 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
>> 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
>> 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
>> 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
>> 0x9f54b20: i32 = undef [ORD=1797] [ID=6]
>> 0x9f54ba8: i32 = FrameIndex<0> [ID=24]
>> 0x9f54b20: i32 = undef [ORD=1797] [ID=6]
>> In function: testVCVTT32TO16Function
>>
>>
>
> I think that support for the half type is only implemented for ARM. 
> Last I tried to use it, I found that none of it works even on x86, and 
> the current handling of the half conversion SDNodes seem to rely on 
> ARM specific assumptions
Have you tried using the @llvm.convert.to/from.fp16 intrinsics instead?
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Andrea Di Biagio

2014-Jul-09 21:20 UTC

head link

[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

Not sure if this can help, but
if you really really want to have minimal half float support on Mips,
then one thing you could try to do is to hack MipsISelLowering.cpp
adding rules to expand float-half conversion SDNodes into library
calls.

+ setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
+ setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);

(The MVT::i32 on the second rule is required because type i16 is
promoted to i32).

If you then convert every occurrence of 'fptrunc' from float to half
with calls to @llvm.convert.to.fp16, then you should be able to
compile (hopefully) with no errors.
That means, in your original example you would convert the following
IR statement:
%Vt3_1 = fptrunc float %Vt_2 to half
into
%Vt3_1 = call i16 @llvm.convert.to.fp16(float %Vt_2)

The downside is that you will have to add definitions for
'__gnu_f2h_ieee' and '__gnu_h2f_ieee' in the compiler runtime.
That is
because the backend will expand all the float-half conversions into
library calls...
This workaround should work assuming that a) you can hack the backend,
and b) it is acceptable (i.e. a reasonable solution in your case) to
have a library call for every float-half conversion in your code.

On Wed, Jul 9, 2014 at 8:51 PM, Matt Arsenault
<Matthew.Arsenault at amd.com> wrote:> I think that support for the half type is only implemented for ARM. Last I
> tried to use it, I found that none of it works even on x86, and the current
> handling of the half conversion SDNodes seem to rely on ARM specific
> assumptions
Just for the record,
since revision 212293 (committed only five days ago), the x86 backend
supports float half conversions.
On x86, if the target has F16C, there are ISel patterns to map
float-half conversions to specific instructions. If there is no F16C
support, then the backend expands float-half conversions into runtime
library calls.

Cheers,
Andrea

Wan, Xiaofei

2014-Jul-10 01:54 UTC

head link

[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

This is fixed by Andrea's patch about one week ago

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of yalong at multicorewareinc.com
Sent: Friday, July 11, 2014 12:45 AM
To: Matt Arsenault; Kevin Qin
Cc: llvmdev
Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

Hi Matt,
    Thank you your replying. I try to use  @llvm.convert.to/from.fp16 intrinsics
before, I also meet "LLVM ERROR: Cannot select:   fp32_to_fp16"
problem, maybe these functions call fptrunc/fpext. Following is detail log:

LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16]
0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20,
0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15]
0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13]
0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9]
0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1]
0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2]
0x9feaab0: i32 = undef [ORD=125117] [ID=4]
In function: internal_function_69
Command exited with non-zero status 1


________________________________
yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>

From: Matt Arsenault<mailto:Matthew.Arsenault at amd.com>
Date: 2014-07-09 12:51
To: yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>;
Kevin Qin<mailto:kevinqindev at gmail.com>
CC: llvmdev<mailto:llvmdev at cs.uiuc.edu>
Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
On 07/09/2014 12:41 PM, Matt Arsenault wrote:
On 07/09/2014 03:30 PM, yalong at multicorewareinc.com<mailto:yalong at
multicorewareinc.com> wrote:
    Thank you Kevin!!!
    If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc 
double %tmp to float" is right, but "fptrunc float %tmp to half"
is wrong). My target platform is MIPS.  The command as following:

NEON:
        vcvtt.f16.f32 s2, s0


llvm Code:

%Vt_2 = load float* %VFP_s0, align 4
%Vt3_1 = fptrunc float %Vt_2 to half
%Vt4_1 = bitcast half %Vt3_1 to i16
%Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>*
%Vrti_1 = load <2 x i16>* %Vt2_2, align 4
%Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1
%Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>*
store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4


Error Log:
LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900,
0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]>
[ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function



I think that support for the half type is only implemented for ARM. Last I tried
to use it, I found that none of it works even on x86, and the current handling
of the half conversion SDNodes seem to rely on ARM specific assumptions

Have you tried using the @llvm.convert.to/from.fp16 intrinsics instead?
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yalong at multicorewareinc.com

2014-Jul-10 16:44 UTC

head link

[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

Hi Matt,    Thank you your replying. I try to use  @llvm.convert.to/from.fp16
intrinsics before, I also meet "LLVM ERROR: Cannot select:  
fp32_to_fp16" problem, maybe these functions call fptrunc/fpext. Following
is detail log:
LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 
0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20,
0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15] 
0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13] 
0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9] 
0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1] 
0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2] 
0x9feaab0: i32 = undef [ORD=125117] [ID=4] 
In function: internal_function_69 
Command exited with non-zero status 1



yalong at multicorewareinc.com
 From: Matt ArsenaultDate: 2014-07-09 12:51To: yalong at multicorewareinc.com;
Kevin QinCC: llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR:
Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] "
problem!!!!!!!!!!!!!!!!!!
  
    
  
  
    On 07/09/2014 12:41 PM, Matt Arsenault
      wrote:

    
    
      
      On 07/09/2014 03:30 PM, yalong at multicorewareinc.com
        wrote:

      
      
        
            Thank you Kevin!!!
            If I use fptrunc and bitcast realise NEON vcvtt ( I can
          sure, "fptrunc  double %tmp to float" is right, but
"fptrunc
          float %tmp to half" is wrong). My target platform is MIPS.
           The command as following:
        

        
        NEON:    
                vcvtt.f16.f32 s2, s0
        

          
        llvm

            Code:
        

            %Vt_2 = load float* %VFP_s0, align 4 

            %Vt3_1 = fptrunc float %Vt_2 to half 

            %Vt4_1 = bitcast half %Vt3_1 to i16 

            %Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>* 

            %Vrti_1 = load <2 x i16>* %Vt2_2, align 4 

            %Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1,
            i32 1 

            %Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>* 

            store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3,
            align 4 

          
        

        
        Error Log:
        
          LLVM ERROR: Cannot select: 0x9f554b0: ch = store
            0x9d0f28c, 0x9f5d900, 0x9f54ba8,
            0x9f54b20<ST2[FixedStack0](align=4), trunc to f16>
            [ID=52] 

            0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40,
            0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51] 

            0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808]
            [ID=31] 

            0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0
            [ORD=1796] [ID=26] 

            0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1] 

            0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17] 

            0x9f54b20: i32 = undef [ORD=1797] [ID=6] 

            0x9f54ba8: i32 = FrameIndex<0> [ID=24] 

            0x9f54b20: i32 = undef [ORD=1797] [ID=6] 

            In function: testVCVTT32TO16Function 

          
        
        

        
        

      
      

      I think that support for the half type is only implemented for
      ARM. Last I tried to use it, I found that none of it works even on
      x86, and the current handling of the half conversion SDNodes seem
      to rely on ARM specific assumptions

    
    

    Have you tried using the @llvm.convert.to/from.fp16 intrinsics
    instead?

  


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yalong at multicorewareinc.com

2014-Jul-10 22:48 UTC

head link

[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!

Hi Andrea    Thank you your replying.    I do like your letter. Add following to
line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can
compile successfully. However, the runtime is not right.
+  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+ 
setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
Robin

yalong at multicorewareinc.com
 From: Andrea Di BiagioDate: 2014-07-09 14:20To: Matt ArsenaultCC: yalong at
multicorewareinc.com; Kevin Qin; llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!!
" LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750
[ID=16] " problem!!!!!!!!!!!!!!!!!!Not sure if this can help, but
if you really really want to have minimal half float support on Mips,
then one thing you could try to do is to hack MipsISelLowering.cpp
adding rules to expand float-half conversion SDNodes into library
calls.

+  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);

(The MVT::i32 on the second rule is required because type i16 is
promoted to i32).

If you then convert every occurrence of 'fptrunc' from float to half
with calls to @llvm.convert.to.fp16, then you should be able to
compile (hopefully) with no errors.
That means, in your original example you would convert the following
IR statement:
  %Vt3_1 = fptrunc float %Vt_2 to half
into
  %Vt3_1 = call i16 @llvm.convert.to.fp16(float %Vt_2)

The downside is that you will have to add definitions for
'__gnu_f2h_ieee' and '__gnu_h2f_ieee' in the compiler runtime.
That is
because the backend will expand all the float-half conversions into
library calls...
This workaround should work assuming that a) you can hack the backend,
and b) it is acceptable (i.e. a reasonable solution in your case) to
have a library call for every float-half conversion in your code.

On Wed, Jul 9, 2014 at 8:51 PM, Matt Arsenault
<Matthew.Arsenault at amd.com> wrote:> I think that support for the half type is only implemented for ARM. Last I
> tried to use it, I found that none of it works even on x86, and the current
> handling of the half conversion SDNodes seem to rely on ARM specific
> assumptions 
Just for the record,
since revision 212293 (committed only five days ago), the x86 backend
supports float half conversions.
On x86, if the target has F16C, there are ISel patterns to map
float-half conversions to specific instructions. If there is no F16C
support, then the backend expands float-half conversions into runtime
library calls.

Cheers,
Andrea

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