search for: fp32_to_fp16

Hi Andrea    Thank you your replying.    I do like your letter. Add following to line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di BiagioDate: 2014-07-09 14:20To: Matt ArsenaultCC: yalong at multicorewareinc.com; Kevin Qin; llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] &...

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following:

...you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com  From: Daniel SandersDate: 2014-07-09 02:05To: yalong at multicorewareinc.com; Kevin QinCC: llvmdevSubject: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi,   NEON is an ARM feature and is therefore not supported by MIPS so I assume you are trying to achieve the same effect. As far as I know, the MIPS backend doesn't support half-precision floating point at the moment.   There is limite...

...vm. I need help. Thank you every! � � I want to realize vcvtt.f16.f32 �NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc ,�I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20, 0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15] 0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13] 0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9] 0x9fbea90: i32 =...

...; [ID=24]  0x9f54b20: i32 = undef [ORD=1797] [ID=6]  In function: testVCVTT32TO16Function  yalong at multicorewareinc.com  From: Kevin QinDate: 2014-07-09 00:03To: yalong at multicorewareinc.comCC: llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!Hi, Can you show us the command line you are using? At least can you tell us the backend you tried on? If you can upload the test case as well, it will be very useful to find out the problem. Regards,Kevin 2014-07-10 1:53 GMT+08:00 yalong at mult...

...missing and it works (or should work?) by converting these to fp32 for the actual calculations? But I'm having problems with this. first I just tried to use fp16 data type, without any support in backend. This was expected to fail. I got error: LLVM ERROR: Cannot select: 0x2f566b0: i32 = fp32_to_fp16 0x2f66bb0 [ID=876] So I created an instruction pattern which matches this fp32_to_fp16 def CFHrf : InstTCE<(outs R32IRegs:$op2), (ins R32FPRegs:$op1), "", [(set R32IRegs:$op2, (fp32_to_fp16 R32FPRegs:$op1))]>; But then I got error /tmp/tcecc-dKBdca/GenInstrInfo.td:30:91: error...

Hi, all: I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4] 0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3] 0x26a66d0: f32 = Register %vreg1 [ID=1] In function: test Anyone know what is the problem; I just suspect intrinsic " llvm.convert.to.fp16" is not well implemented? Attaching my test: #t...