search for: __gnu_f2h_ieee

Hi all, -soft-float can not be rightly use by llc. All float function operation will call soft float, but not hard. My mips device cannot support half float type, so I hack the llvm, and add soft half float and add -soft-float option. I add the function define for __gnu_f2h_ieee() and __gnu_h2f_ieee (), and it can call the soft half float. However, all the others function about float also call the soft float, how I do make only __gnu_f2h_ieee() use soft float, other use hard float??? Thank you all !! Cheers, Robin -------------- next part -------------- An HT...

...hould be able to compile (hopefully) with no errors. That means, in your original example you would convert the following IR statement:   %Vt3_1 = fptrunc float %Vt_2 to half into   %Vt3_1 = call i16 @llvm.convert.to.fp16(float %Vt_2)   The downside is that you will have to add definitions for '__gnu_f2h_ieee' and '__gnu_h2f_ieee' in the compiler runtime. That is because the backend will expand all the float-half conversions into library calls... This workaround should work assuming that a) you can hack the backend, and b) it is acceptable (i.e. a reasonable solution in your case) to have a...

Hi, all: I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4] 0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3] 0x26a66d0: f32 = Register %vreg1 [ID=1] In function: test

...fset 16 movzwl y(%rip), %edi callq __gnu_h2f_ieee movss %xmm0, 4(%rsp) # 4-byte Spill movzwl z(%rip), %edi callq __gnu_h2f_ieee addss 4(%rsp), %xmm0 # 4-byte Folded Reload movss %xmm0, 4(%rsp) # 4-byte Spill movzwl w(%rip), %edi callq __gnu_h2f_ieee addss 4(%rsp), %xmm0 # 4-byte Folded Reload callq __gnu_f2h_ieee movw %ax, x(%rip) popq %rax I assumed SelectionDAG should produce something equivalent to the original clang code with 4 total extends to f32 and 2 truncates. Instead we got 3 extends and 1 truncate. So we lost the intermediate rounding between the 2 adds that was in the original clang IR. I bel...

...Spill > > movzwl z(%rip), %edi > > callq __gnu_h2f_ieee > > addss 4(%rsp), %xmm0 # 4-byte Folded Reload > > movss %xmm0, 4(%rsp) # 4-byte Spill > > movzwl w(%rip), %edi > > callq __gnu_h2f_ieee > > addss 4(%rsp), %xmm0 # 4-byte Folded Reload > > callq __gnu_f2h_ieee > > movw %ax, x(%rip) > > popq %rax > > > > > > I assumed SelectionDAG should produce something equivalent to the original > clang code with 4 total extends to f32 and 2 truncates. Instead we got 3 > extends and 1 truncate. So we lost the intermediate rounding be...

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following: