In the representation of the code after instruction selection (but before register allocation), in a MachineBasicBlock: How/where is the result of a machine instruction linked to one of the machine operands of a subsequent machine instruction? Asked differently: How/where are the links of the DAG implemented (specially between MachineInstr and MachineOperand)? Frank
The missing information was that machine instructions employ a def/use semantic for their operands. The 'links' between input and output of instructions are the virtual registers, first 'defined' (as output) and in a subsequent consumer instruction 'used' (as input). Frank On 29/05/13 09:58, Frank Winter wrote:> In the representation of the code after instruction selection (but > before register allocation), in a MachineBasicBlock: > How/where is the result of a machine instruction linked to one of the > machine operands of a subsequent machine instruction? > Asked differently: How/where are the links of the DAG implemented > (specially between MachineInstr and MachineOperand)? > > Frank >
Possibly Parallel Threads
- [LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
- [LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
- [LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
- [LLVMdev] InsertBranch called unconditionally?
- [LLVMdev] RFC: MachineInstr Annotations