Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] Link between MachineInstr and MachineOperand"
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Hi Sergei,
our use of target flags will be on immediate register operands if I am
not mistaken (and if not we can always encode it as such)?
I guess you are refering to the hexagon backend needing to distinguish
between instances of an instruction that uses a constant value that
can fit into the 4 byte of the instruction and one that encodes the
immediate in an extra instruction slot (what we
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Jakob and anyone else who might be interested...
Base on this patch back in August, I sense some need to double check with
you whether it is OK to start making a heavy use of MachineOperand
TargetFlags?
We do seem to have a compelling reason for it in Hexagon, and I wanted to
make sure that it is OK with everyone. I plan to use it for attributing
target specific info to MOs and in more general
2012 Nov 27
1
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
Hi Craig,
I updated from the trunk some minutes ago, and thus got the "explicit". PrintReg constructor. When I do not include raw_ostream.h after including Debug.h in the backend cpp files, I now get compilation errors, not only when trying to print floats but also in other places. For example, for the code
bool ADRESRegisterInfo::hasReservedCallFrame(const MachineFunction &MF)
2006 Oct 24
1
[LLVMdev] InsertBranch called unconditionally?
According to the docs, InsertBranch should only be called if
AnalyzeBranch returns success. But in targets (like ARM or Sparc) that
don't implement them, the following test fails:
-----------------------------------
void %__gcov_init() {
entry:
switch uint 0, label %cond_true.i [
uint 0, label %UnifiedReturnBlock
uint 875573313, label
2009 Jul 31
3
[LLVMdev] RFC: MachineInstr Annotations
I'm getting to the point where I want to contribute some more
MachineInstr comment support for things like spills. As we've
discussed before, we don't have all of the information available
in AsmPrinter to synthesize the kind of comments that can be
helpful for debugging performance issues with register allocators
(our primary use for these kinds of comments).
In order to get this
2019 May 10
2
[Pipeliner] MachinePipeliner TargetInstrInfo hooks need more information?
Hello,
I'm working on integrating the MachinePipeliner.cpp pass into our VLIW
backend, and so far we've managed to get it working with some nice
speedups.
Unlike Hexagon however, our backend doesn't generate hardware loop
instructions and so all our loops are a combination of induction
variables, comparisons and branches. So when it came to implementing
reduceLoopCount for our
2012 Oct 29
2
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Arnold,
I wanted to hear from Jacob is the original patch in question still needed,
since our use of this field could surpass const extenders and could
potentially include MO_Register.
Jacob,
Can you please comment? Thanks.
Sergei
---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
> -----Original Message-----
> From: Arnold
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
This seems a very natural approach but I probably am having a trouble with
the iterator invalidation. However, looking at other peephole optimizers
passes, I couldn't see how to do this:
#define BUILD_INS(opcode, new_reg, i) \
BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \
.addReg(X86::new_reg, kill).addImm(i)
for
2015 Aug 11
3
Working with X86 registers in MachineInstr
Hi all,
I am attempting to implement the "reaching definitions" data-flow algorithm
on (X86) MachineBasicBlocks for an analysis pass. To do this, I need to
compute gen/kill sets for machine basic blocks. To start with, I am only
considering the general-purpose registers, RAX-R15 and their sub-registers.
Thus, I need to examine each MachineInstr to determine which register(s) it
2009 Jul 17
2
[LLVMdev] Bug in LiveIntervals? Please Examine
In LiveIntervals::processImplicitDefs() we have this:
for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
UE = mri_->use_end(); UI != UE; ) {
MachineOperand &RMO = UI.getOperand();
MachineInstr *RMI = &*UI;
++UI;
MachineBasicBlock *RMBB = RMI->getParent();
if (RMBB == MBB)
continue;
const
2015 Sep 08
4
Inserting MachineInstr's
Hi,
I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g.
Replace:
fmuls %f20,%f21,%f8
with the
2005 Sep 27
1
[LLVMdev] How does the memory of MachineInstr objects are managed?
A question about how the memory of object in LLVM are managed.
I dived in some source files but still don't have any idea how the
memory of MachineInstr object are managed. It doesn't look like
reference counting.
I'm writing an instruction scheudling code, the new order of
MachineInstr* in a MachineBasicBlock is stored in a "schedule". All
MachineInstr* in
2010 May 18
3
[LLVMdev] selection dag speedups / llc speedups
Here are some recent stats of the fast vs local vs linear scan at O0 on "opt
-std-compile-opts" processed bitcode files. The fast regalloc is still
certainly faster at codegen than local with such bitcode files. Let me know
if the link doesn't work:
https://spreadsheets.google.com/a/google.com/ccc?key=0At5EJFcCBf-wdDgtd2FoZjU4bFBzcFBtT25rQkgzMEE&hl=en
Misc stuff: I ran into an
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
Hi,
I'm lowering some of the logical operators (by example the | operator) on integer32.
Sadly my target only provide native instruction on high and low parts of 32 bits registers.
So, I have to generate a sequence of two native instructions (LOR followed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins
2006 Aug 14
2
[LLVMdev] Folding instructions
> Hi Fernando,
>
> It's hard to say exactly what's happening because I don't know your
> code (though, from the stack trace, it seems like there's some sort
> of memory debacle), but looking at the comment in the
> LiveVariableAnalysis.cpp file where it's folding memory operands, it
> might explain somethings better:
>
> // Folding the
2015 Jun 16
2
[LLVMdev] Replacing a Reg MachineOperand with a non-Reg MachineOperand?
I'm not sure I understand what your problem is, but are you calling the
removeRegOperandFromUseList on the machine operand after changing it to GA?
You have to call removeRegOperandFromUseList before changing the operand's
type, as it expects a register operand.
2015-06-16 10:05 GMT-07:00 Ryan Taylor <ryta1203 at gmail.com>:
> @Alex: Thanks. setOffset(0) eliminated any previous
2008 Sep 24
2
[LLVMdev] Determining the register type of a MachineOperand
This only has the register class information, not the register type
information.
My register class has multiple register types and I need to know how to
differentiate which register type of my register class of the current
register.
The information in the MVT data type is what I need, i.e. the position
in the GPRVT array of each register.
Something equivalent to MVT getValueType() but for
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
On Oct 29, 2012, at 3:28 PM, "Sergei Larin" <slarin at codeaurora.org> wrote:
> Arnold,
>
> I wanted to hear from Jacob is the original patch in question still needed,
> since our use of this field could surpass const extenders and could
> potentially include MO_Register.
>
> Jacob,
>
> Can you please comment? Thanks.
I don't really have
2011 Jan 29
1
[LLVMdev] The type or size of virtual registers in machineinstr
Hi,
I want to know what is the type or size of a virtual register in a
Machineinstr::MachineOperand (If this MachineOperand is a register). For
example, what is the size of reg16385 in the following MachineInstr. I know
now in the llvm bitcode, the type of a Instruction could be obtained from
the Value::GetType(), but what is the counterpart in MachineInstr (not
derived from class Value)?
2008 Sep 24
0
[LLVMdev] Determining the register type of a MachineOperand
You can get to the MachineInstr from a MachineOperand. Then get to its
TargetInstrDesc and TargetOperandInfo which has register class
information.
Evan
On Sep 23, 2008, at 12:44 PM, Villmow, Micah wrote:
> How do I determine what type of register(i.e. i32, f32, etc..) I am
> accessing from a MachineOperand? I.e. how do I get to the MVT
> struct, or equivalent information, from