llvm dev - Sep 2012 - [LLVMdev] Distinguish variadic register defines/uses in MCInstrDesc?

Hello,

I'm currently working on a rich disassembler for some ARM/Thumb environment.
I wanted to keep most classes independent of the architecture, so I use 
MCInstrInfo and MCInstrAnalysis to find branch instructions (and other 
instructions writing to the program counter) and to differentiate between 
register definitions and uses to track all instructions the branch depends on.

This works well for most cases, except if there are Thumb pop instructions 
involved.

Pop has a variable number of output registers, so MCInstrDesc::getNumDefs 
returns zero and, as far as I can see, in the tablegen files
'variable_ops' is
always in the 'ins' list and MCInstrDesc only provides isVariadic();

My current workaround is to assume that all variadic arguments of instructions 
that have zero register definitions but are marked as mayLoad are register 
definitions. I'm not very happy with this solution.

Is it possible to extend LLVM to check if 'variable_ops' is in
'ins' and/or
'outs' in tablegen, so that MCInstrDesc could provide something like 
hasVariadicDefs() and hasVariadicUses()?

That way handling variadic instructions when disassembling would be much 
easier and only instructions with variadic uses and defines would need 
explicit special casing - if they even exist.

Thanks,
Christoph

On Sep 24, 2012, at 6:39 PM, Christoph Grenz <christophg+llvm at
grenz-bonn.de> wrote:
> Is it possible to extend LLVM to check if 'variable_ops' is in
'ins' and/or
> 'outs' in tablegen, so that MCInstrDesc could provide something
like
> hasVariadicDefs() and hasVariadicUses()?
> 
> That way handling variadic instructions when disassembling would be much 
> easier and only instructions with variadic uses and defines would need 
> explicit special casing - if they even exist.
Hi Christoph,

As you noticed, MCInstrDesc doesn't distinguish between variadic uses and
defs. Since variadic instructions will always require some kind of special
handling, it doesn't seem worthwhile to make the model more detailed.

I think your current workaround sounds fine.

/jakob

Am Mittwoch, 26. September 2012, 11:18:20 schrieb Jakob Stoklund
Olesen:
> Hi Christoph,
> 
> As you noticed, MCInstrDesc doesn't distinguish between variadic uses
and
> defs. Since variadic instructions will always require some kind of special
> handling, it doesn't seem worthwhile to make the model more detailed.
I don't see what makes them so different from other instructions.
MCInstrDesc provides the information which operands are defines and which uses 
for all other instruction types and for variadic there are only three possible 
cases:
* All variadic registers are uses (push/stm on ARM)
* All variadic registers are defines (pop/ldm)
* uses and defines are mixed.

I think variable_ops on x86 RET can also be modeled as the first case.

The first two cases don't need any special handling. The start and count of 
variadic operands is known through MCInstrDesc and 
MCInstruction::getNumOperands(). So I can handle them like any other 
instruction if I know which case applies. Only the third case really needs 
special handling and I couldn't find an instruction that falls into this
case.
> I think your current workaround sounds fine.
> 
> /jakob
Christoph