search for: mcinstruction

...push/stm on ARM) * All variadic registers are defines (pop/ldm) * uses and defines are mixed. I think variable_ops on x86 RET can also be modeled as the first case. The first two cases don't need any special handling. The start and count of variadic operands is known through MCInstrDesc and MCInstruction::getNumOperands(). So I can handle them like any other instruction if I know which case applies. Only the third case really needs special handling and I couldn't find an instruction that falls into this case. > I think your current workaround sounds fine. > > /jakob Christoph

...egisters are defines (pop/ldm) > * uses and defines are mixed. > > I think variable_ops on x86 RET can also be modeled as the first case. > > The first two cases don't need any special handling. The start and count of > variadic operands is known through MCInstrDesc and > MCInstruction::getNumOperands(). So I can handle them like any other > instruction if I know which case applies. Only the third case really needs > special handling and I couldn't find an instruction that falls into this > case. > > I think your current workaround sounds fine. > > >...

On Sep 24, 2012, at 6:39 PM, Christoph Grenz <christophg+llvm at grenz-bonn.de> wrote: > Is it possible to extend LLVM to check if 'variable_ops' is in 'ins' and/or > 'outs' in tablegen, so that MCInstrDesc could provide something like > hasVariadicDefs() and hasVariadicUses()? > > That way handling variadic instructions when disassembling would be

On 01/29/2014 03:39 PM, Rafael Espíndola wrote: >> So explain to me how this mechanism would work. >> >> As I'm processing a single mips16 function, I realize that I need to create >> one or more mips32 helper functions. >> >> I'm in a function pass. So I'm not supposed to be creating new functions, as >> far as I understand. >> >>

Hello, I'm currently working on a rich disassembler for some ARM/Thumb environment. I wanted to keep most classes independent of the architecture, so I use MCInstrInfo and MCInstrAnalysis to find branch instructions (and other instructions writing to the program counter) and to differentiate between register definitions and uses to track all instructions the branch depends on. This works

...has not been corrupted during execution. This is supported on both X86-64 and AArch64. [r329139](https://reviews.llvm.org/rL329139),[r329236](https://reviews.llvm.org/rL329236). * Codegen support for the RISC-V 'C' (compressed) instruction set extension has landed. When possible, a 32-bit MCInstruction is converted to the 16-bit equivalent. [r329455](https://reviews.llvm.org/rL329455). * A new `upate_analyze_test_checks.py` script has been added. This aids the generation of checks in cost model tests. [r329390](https://reviews.llvm.org/rL329390). * Support was added for llvm.coro.noop intrinsic...