hi,
i have a simple code like below, in wich variable "aaa" does not alias
to "bbb".
i use TBAA to specify this, please see the code.
then i ran this code thru LLVM optimization, and i expected that the
second "store" instruction is eliminated.
however, i am wrong: the second "store" instruction is still there
after optimization.
perhaps my TBAA setup is wrong somewhere? any hint, please?
thanks!
Jun
@aaa = external global i32
@bbb = external global i32
....
%0 = load i32* @aaa, !tbaa !1
%1 = load i32* @bbb, !tbaa !2
%2 = add i32 %0, %1
store i32 %2, i32* @aaa, !tbaa !2
; below line should be eliminated with optimization
store i32 %1, i32* @bbb, !tbaa !1 ; <==== WHY
optimization CANNOT ELIMINATE this insn?
...
!tbaa = !{!0, !1, !2}
!0 = metadata !{metadata !"tbaa_root"}
!1 = metadata !{metadata !"aaa", metadata !0}
!2 = metadata !{metadata !"bbb", metadata !0}
Hi Jun, did you tell "opt" to make use of TBAA? Also, please give complete IR that people can use to reproduce, and instructions on how to reproduce (eg how to run opt). Ciao, Duncan.> i have a simple code like below, in wich variable "aaa" does not alias > to "bbb". > i use TBAA to specify this, please see the code. > > then i ran this code thru LLVM optimization, and i expected that the > second "store" instruction is eliminated. > however, i am wrong: the second "store" instruction is still there > after optimization. > > perhaps my TBAA setup is wrong somewhere? any hint, please? > > thanks! > Jun > > > @aaa = external global i32 > @bbb = external global i32 > > .... > %0 = load i32* @aaa, !tbaa !1 > %1 = load i32* @bbb, !tbaa !2 > %2 = add i32 %0, %1 > store i32 %2, i32* @aaa, !tbaa !2 > > ; below line should be eliminated with optimization > store i32 %1, i32* @bbb, !tbaa !1 ; <==== WHY > optimization CANNOT ELIMINATE this insn? > > ... > !tbaa = !{!0, !1, !2} > !0 = metadata !{metadata !"tbaa_root"} > !1 = metadata !{metadata !"aaa", metadata !0} > !2 = metadata !{metadata !"bbb", metadata !0} > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >
2012/9/20 Jun Koi <junkoi2004 at gmail.com>:> %0 = load i32* @aaa, !tbaa !1 > %1 = load i32* @bbb, !tbaa !2> store i32 %2, i32* @aaa, !tbaa !2 > store i32 %1, i32* @bbb, !tbaa !1 ; <==== WHYWhy are you tagging each "store" with different classes against corresponding "load(s)"?> store i32 %2, i32* @aaa, !tbaa !1 > store i32 %1, i32* @bbb, !tbaa !2I guess it would be more expected. ...Takumi
On Thu, Sep 20, 2012 at 5:18 PM, Duncan Sands <baldrick at free.fr> wrote:> Hi Jun, did you tell "opt" to make use of TBAA? Also, please give complete > IR > that people can use to reproduce, and instructions on how to reproduce (eg > how > to run opt). >actually, i am still confused on which options should be given to "opt" for it to use TBAA. any hint? of course, we can simply use -O3, but i want to pinpoint exactly which passes are necessary for TBAA optimization to work. thanks, Jun>> i have a simple code like below, in wich variable "aaa" does not alias >> to "bbb". >> i use TBAA to specify this, please see the code. >> >> then i ran this code thru LLVM optimization, and i expected that the >> second "store" instruction is eliminated. >> however, i am wrong: the second "store" instruction is still there >> after optimization. >> >> perhaps my TBAA setup is wrong somewhere? any hint, please? >> >> thanks! >> Jun >> >> >> @aaa = external global i32 >> @bbb = external global i32 >> >> .... >> %0 = load i32* @aaa, !tbaa !1 >> %1 = load i32* @bbb, !tbaa !2 >> %2 = add i32 %0, %1 >> store i32 %2, i32* @aaa, !tbaa !2 >> >> ; below line should be eliminated with optimization >> store i32 %1, i32* @bbb, !tbaa !1 ; <==== WHY >> optimization CANNOT ELIMINATE this insn? >> >> ... >> !tbaa = !{!0, !1, !2} >> !0 = metadata !{metadata !"tbaa_root"} >> !1 = metadata !{metadata !"aaa", metadata !0} >> !2 = metadata !{metadata !"bbb", metadata !0} >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev