Displaying 20 results from an estimated 566 matches for "insn".
Did you mean:
ins
2011 Apr 07
0
[LLVMdev] dragonegg-2.9 build fail
...0/4.5.2/plugin/include/tm.h:17,
from /sw/lib/gcc4.5/lib/gcc/x86_64-apple-darwin10.5.0/4.5.2/plugin/include/Target.h:52,
from /sw/src/fink.build/dragonegg-gcc45-2.9-1/dragonegg-2.9/Backend.cpp:31:
/sw/lib/gcc4.5/lib/gcc/x86_64-apple-darwin10.5.0/4.5.2/plugin/include/insn-flags.h:2011: error: 'rtx' does not name a type
/sw/lib/gcc4.5/lib/gcc/x86_64-apple-darwin10.5.0/4.5.2/plugin/include/insn-flags.h:2012: error: 'rtx' does not name a type
/sw/lib/gcc4.5/lib/gcc/x86_64-apple-darwin10.5.0/4.5.2/plugin/include/insn-flags.h:2013: error: 'rtx' do...
2020 Apr 28
0
[PATCH v3 10/75] x86/insn: Add insn_rep_prefix() helper
From: Joerg Roedel <jroedel at suse.de>
Add a function to check whether an instruction has a REP prefix.
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/insn-eval.h | 1 +
arch/x86/lib/insn-eval.c | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index 1e343010129e..a63b29466032 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/as...
2020 Apr 28
0
[PATCH v3 08/75] x86/umip: Factor out instruction decoding
From: Joerg Roedel <jroedel at suse.de>
Factor out the code used to decode an instruction with the correct
address and operand sizes to a helper function.
No functional changes.
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/insn-eval.h | 2 ++
arch/x86/kernel/umip.c | 23 +---------------
arch/x86/lib/insn-eval.c | 45 ++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index b8b9ef1bbd06..b4...
2010 Aug 27
0
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On 08/26/2010 13:17, Dale Johannesen wrote:
>>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>,
>>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ...
>>
>> Odd. I thought TCReturn was being lowered. At any rate can you file
>> a bug with the .ll file that causes this...
2010 Aug 26
2
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
...ppens?
>>> (just change the line above the error message to print it out to
>>> errs()).
>>>
>>> It basically means that a pseudo wasn't lowered to something that
>>> the jit can output before the jit was run. Is this on ToT?
>>
>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>,
>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ...
>
> Odd. I thought TCReturn was being lowered. At any rate can you
> file a bug with the .ll file that causes this?
It should b...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
...:emitMINMAX(const Instruction *i)
else
if (!isFloatType(i->dType))
op |= isSignedType(i->dType) ? 0x23 : 0x03;
+ if (i->dType == TYPE_F64)
+ op |= 0x01;
emitForm_A(i, op);
emitNegAbs12(i);
@@ -2242,20 +2296,26 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn->dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
-...
2013 Sep 12
1
[LLVMdev] [patch] remove redundant code in X86DisassemblerDecoder.c
...86DisassemblerDecoder.c
b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
index 20e61da..3932ea1 100644
--- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
+++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
@@ -550,11 +550,6 @@ static int readPrefixes(struct InternalInstruction*
insn) {
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
- } else if (insn->rexPrefix) {
- insn->registerSize = (hasOpSize ? 2 : 4);
- insn->addressSize = (hasAdSize ? 4 : 8);
-...
2013 Jun 26
1
[LLVMdev] Auxiliary operand types for disassembler.
On 06/25/2013 04:46 PM, Jim Grosbach wrote:
> Hi Sid,
>
> This feels like it’s exposing too much of the disassembler internals
> into the MCOperand representation. I’m not sure I follow why that’s
> necessary. Can you elaborate a bit?
>
A packet contains 1-4 insns and until the contents of the entire packet
are known the meaning of any individual insn is not known with 100%
certainty. Adding the auxiliary operand was a way for the printer to
accumulate this information as the packet is being read.
An alternative is to pass the raw insn to the target pr...
2013 Jun 25
2
[LLVMdev] Auxiliary operand types for disassembler.
I'm working on a disassembler for hexagon (vliw) architecture and I
would like to add an additional operand type, "kAux" to the MCOperand class.
The reason for this is that each insn has parse bits which are not
explicit operands and have differing meanings based on the insn's
location within the packet and the number of insns inside the packet.
In order for the disassembler to correctly represent the insn it needs
to accumulate the series of insns that form the packet....
2010 Dec 16
1
[LLVMdev] x86 disassembler: if-statement with redundant branch
...llvm-2.8/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
--- llvm-2.8.orig/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c 2010-05-06 22:59:00.000000000 +0200
+++ llvm-2.8/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c 2010-12-16 16:24:28.583323293 +0100
@@ -412,11 +412,6 @@
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
- } else if (insn->rexPrefix) {
- insn->registerSize = (hasOpSize ? 2 : 4);
- insn->addressSize = (hasAdSize ? 4 : 8);
- insn->dis...
2010 Aug 27
2
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On Aug 26, 2010, at 11:34 PMPDT, Yuri wrote:
> On 08/26/2010 13:17, Dale Johannesen wrote:
>>>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>,
>>>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ...
>>>
>>> Odd. I thought TCReturn was being lowered. At any rate can you
>>> file a bug with the .ll fil...
2013 Jun 25
0
[LLVMdev] Auxiliary operand types for disassembler.
...m
On Jun 25, 2013, at 8:24 AM, Sid Manning <sidneym at codeaurora.org> wrote:
>
> I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type, "kAux" to the MCOperand class.
>
> The reason for this is that each insn has parse bits which are not explicit operands and have differing meanings based on the insn's location within the packet and the number of insns inside the packet. In order for the disassembler to correctly represent the insn it needs to accumulate the series of insns that form the packet. Onl...
2014 May 10
1
[PATCH] nv50/ir: make sure to reverse cond codes on all the OP_SET variants
...v50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index c89e1c3..cdae3c8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -187,7 +187,8 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
return;
}
- if (insn->op == OP_SET)
+ if (insn->op == OP_SET || insn->op == OP_SET_AND ||
+ insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
insn->asCmp()->setCond = reverseCondCode(insn->asCmp()->setCond);
else
if (insn->op == OP...
2009 Sep 10
0
[PATCH 01/13] nv50: extend insn src mask function
Extend its usage to avoiding e.g. emission of negation
instructions in tx_insn for sources we don't need.
---
src/gallium/drivers/nv50/nv50_program.c | 118 +++++++++++++++++++------------
1 files changed, 72 insertions(+), 46 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 4a83852..a6c70ae 100644
--- a/...
2012 Mar 02
3
[LLVMdev] how to annotate assembler
...fi_endproc
Now I may look into config/i386/i386.md, and look for mentioned
*pushdi2_rex64, movdi_1_rex64, floatdidf2_sse_interunit and other
patterns and study how they work.
How to make the same annotation for clang output assembler code?
test:
.Leh_func_begin1:
pushq %rbp # ??? what insn in X86InstrInfo.td?
.Llabel1:
movq %rsp, %rbp # ??? what insn in X86InstrInfo.td?
.Llabel2:
movq %rdi, -16(%rbp) # ??? what insn in X86InstrInfo.td?
movq -16(%rbp), %rax # ??? what insn in X86InstrInfo.td?
cvtsi2sdq %rax, %xmm0 # ??? what insn in X86InstrInfo.td?
movsd %xmm0, -8(%r...
2014 Mar 31
2
[LLVMdev] registerSize on X86 confused?
Hi,
In file X86DisassemblerDecoder.c, we have function readPrefixes() with
below code:
.....
} else if (insn->mode == MODE_32BIT) {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAdSize ? 2 : 4);
insn->displacementSize = (hasAdSize ? 2 : 4);
insn->immediateSize = (hasOpSize ? 2 : 4);
}
....
This is confused to me: so we have register...
2010 Aug 27
0
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On Aug 27, 2010, at 10:49 AM, Dale Johannesen wrote:
>
> On Aug 26, 2010, at 11:34 PMPDT, Yuri wrote:
>
>> On 08/26/2010 13:17, Dale Johannesen wrote:
>>>>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ...
>>>>
>>>> Odd. I thought TCReturn was being lowered. At any rate can you file a bug with the .ll file that causes this?
>&...
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
...4
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_AND:
{
- CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
- if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
- return;
- if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
- return;
- if (imm0.reg.data.f32 != 1.0)
- return;
- if (i->getSrc(t)->get...
2017 Jun 11
0
[RFC 4/9] tgsi: populate precise
...header);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 5bd779728a..56db2252c5 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -1213,6 +1213,7 @@ struct ureg_emit_insn_result
ureg_emit_insn(struct ureg_program *ureg,
unsigned opcode,
boolean saturate,
+ unsigned precise,
unsigned num_dst,
unsigned num_src)
{
@@ -1226,6 +1227,7 @@ ureg_emit_insn(struct ureg_program *ureg,
out[0].in...
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
..._ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 0ff5e5d..56033f1 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -567,6 +567,7 @@ public:
inline Value *rep() const { return join; }
+ inline Instruction *getUniqueInsnMerged() const;
inline Instruction *getUniqueInsn() const;
inline Instruction *getInsn() const; // use when uniqueness is certain
@@ -583,11 +584,11 @@ public:
static inline Value *get(Iterator&);
std::tr1::unordered_set<ValueRef *> uses;
- std::list<ValueDef *>...