llvm dev - Aug 2012 - [LLVMdev] llvm microblaze port - severe data hazards

Hi, i'm working on a microblaze port extremely similar to microblaze that
only
has data hazards. The advice given to look at PPC and ARM is poor because 
neither of them check for data dependencies and are entirely complicated and 
different. The port has a 5 stage pipeline where the result of instruction can 
only be used at stage 3 and 5 only whereas load and store instructions require 4
cycles. That means that if there was a code such as 
code 1                                       code 2
lwi r3, r0, 4                          addik r3, r4, 5 
cmp r4, r3, 5                          swi r3, r0, 12
                                       swi r3, r0, 16
would cause cmp and swi r3,r0,12 to use the old value of r3.
It should be
lwi r3, r0, 4                         addik r3, r4, 5
nop                                   nop
nop                                   swi r3, r0, 12
nop                                   nop
cmp r4, r3, 5                         swi r3, r0, 16

Due to the pipeline it is correct to have
lwi, r3, r0, 4
some instruction not writing to r3
some instruction not writing to r3
swi, r3, r0, 8 (will store the old r3 value)
cmp r4, r3, 5 (will use the new r3 value)

I've already tried adapting PPC hazard but i cant make heads or tails of it
and
even make it work.
I'd also like to know if hazard recognisers are used when filling in delay 
slots. The port fills in up to 3 delay slots the same way as it would fill 1 
delay slot microblaze (moves instruction or nop if cant find any
) in order to prevent hazards.
I'd appreciate any help on this.
Thank you.