Displaying 7 results from an estimated 7 matches for "addik".
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2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...sltiu $2, $1, 1
move $sp, $fp
lw $fp, 20($sp)
addiu $sp, $sp, 24
jr $ra
nop
The two comparisons are very similar.
For the Microblaze, I get:
signed long long:
main:
.frame r19,40,r15
.mask 0x80000
addik r1, r1, -40
swi r19, r1, 4
add r19, r1, r0
swi r0, r19, 8
addik r3, r0, 100
swi r3, r19, 20
swi r0, r19, 16
addik r3, r0, -2147483648
swi r3, r19, 24
swi r0, r19, 2...
2017 Dec 11
2
target porting : objdump is not giving proper registers.
...er numbers when we have generated assembly files
through clang but
when we generated dump files from object file then we didn't see expected
register numbers.
Note : all registers are replaced with R0
*Disassembly of section .text:00000000 <main>: 0: 3000ffcc addik
r0, r0, -52 4: f8000000 swi r0, r0, 0 8: 10000000
addk r0, r0, r0 c: f800002c swi r0, r0, 44 10:
3000000a addik r0, r0, 10 14: f8000028 swi r0, r0,
40 18: 3000000f addik r0, r0, 15 1c: f8000024 swi
r0, r0, 36 2...
2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...ss;
...
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
has something similar.
In Mblaze case I can see the result being used the very next cycle
mul *r3*, r6, r5
addik r3,* r3*, 4
similarly for my target (instead of 17 I'm specifying 2 above) and for Mips
I get the same result. Same for loads where I'm also specifying a larger
latency
What would be the right way to specify a latency of 2 with 1 clk initiation
interval for instance
Thanks
Miguel
---...
2012 Aug 12
0
[LLVMdev] llvm microblaze port - severe data hazards
...ent. The port has a 5 stage pipeline where the result of instruction can
only be used at stage 3 and 5 only whereas load and store instructions require 4
cycles. That means that if there was a code such as
code 1 code 2
lwi r3, r0, 4 addik r3, r4, 5
cmp r4, r3, 5 swi r3, r0, 12
swi r3, r0, 16
would cause cmp and swi r3,r0,12 to use the old value of r3.
It should be
lwi r3, r0, 4 addik r3, r4, 5
nop nop
nop...
2011 Aug 16
0
[LLVMdev] Question on instruction itineraries
...l , [InstrStage<17, [IMULDIV]>]>,
>
> Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
> has something similar.
Yes.
> In Mblaze case I can see the result being used the very next cycle
> mul r3, r6, r5
> addik r3, r3, 4
> similarly for my target (instead of 17 I'm specifying 2 above) and for Mips
> I get the same result. Same for loads where I'm also specifying a larger
> latency
Specifying a schedule doesn't really do anything if there isn't
anything which can be scheduled...
2012 Oct 21
2
[LLVMdev] Need help trying to generate mblaze code.
Hello,
this is a very dump question, I hope to do more valuable question soon, but
for now I'm just trying to run a simple hello world in C for clang and llvm
to the target mblaze, but is not working.
( I need to change the compiler in the next stage)
I past all the weekend tried to run this, and I was unable, I did the build
of llVM/clang, but no bin was generate, only silly folder that I
2011 Aug 17
1
[LLVMdev] Question on instruction itineraries
...]>,
> >
> > Does that mean Mul's are expected to have a latency of 17 clks ? Mips
> target
> > has something similar.
>
> Yes.
>
> > In Mblaze case I can see the result being used the very next cycle
> > mul r3, r6, r5
> > addik r3, r3, 4
> > similarly for my target (instead of 17 I'm specifying 2 above) and for
> Mips
> > I get the same result. Same for loads where I'm also specifying a larger
> > latency
>
> Specifying a schedule doesn't really do anything if there isn't
>...