search for: microblaz

Hello, i am trying to create a LLVM stack to cross compile c code targeting the xilinx microblaze. I built LLVM configured with target=microblaze however cland doesn't like it. When i try to emit llvm code i get the following error: unknown target triple 'microblaze-unknown-none', please use -triple or -arch How should i configure my LLVM stack and then how should i run the too...

I have been working on a LLVM backend for the MicroBlaze soft-processor: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze Attached is the initial MicroBlaze patch. It does the following: 1. Adds mblaze as a target in configure and configure.ac 2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and i...

I have been working on a LLVM backend for the MicroBlaze (http://en.wikipedia.org/wiki/MicroBlaze ) soft-processor. At this point the backend is partially functional but by no means complete. I was curious as to wether the LLVM developers would prefer to merge the backend into the main tree now and then accept patches on the backend until it was...

Hi Fivos, LLVM refers to the target as "mblaze" for -target. -Jim On Jun 26, 2012, at 8:42 AM, Fivos <fivosz at gmail.com> wrote: > Hello, > > i am trying to create a LLVM stack to cross compile c code targeting the > xilinx microblaze. > > I built LLVM configured with target=microblaze however cland doesn't > like it. When i try to emit llvm code i get the following > error: unknown target triple 'microblaze-unknown-none', please use > -triple or -arch > > How should i configure my LLVM stac...

conmfigure does not accept mblaze nor mblaze-elf as target. checking target system type... Invalid configuration `mblaze': machine `mblaze' not recognized configure: error: /bin/bash ../../spare/llvm/autoconf/config.sub mblaze failed However with microblaze it proceeds fine. But when i try to use clang i get: clang: error: 'microblaze-unknown-none': unable to pass LLVM bit-code files to linker if i give mblaze as the target it still fails with: clang: error: 'mblaze': unable to pass LLVM bit-code files to linker I also built LLVM w...

On Jan 29, 2010, at 9:42 AM, Wesley Peck wrote: > I have been working on a LLVM backend for the MicroBlaze soft-processor: > http://www.xilinx.com/tools/microblaze.htm > http://en.wikipedia.org/wiki/MicroBlaze Very Cool! > Attached is the initial MicroBlaze patch. It does the following: > 1. Adds mblaze as a target in configure and configure.ac > 2. Adds mblaze specific intrinsics in i...

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

...ches. Also indirect calls and indirect branches. Have you tries running Codegen/generic through your back end? That should give you some more test cases. > Some "feature" tests can be found inside other directories as well, > e.g. msp430 / systemz. > > Are you planning to add microblaze description to clang? C compiler > can speed up testing alot :) I already have a microblaze description in clang but I have not tested it as much so I have not submitted a patch for it yet. > > More comments: >> +SDValue MBlazeTargetLowering:: >> +LowerDYNAMIC_STACKALLOC(SD...

...s, switches and branches. Also indirect calls and indirect branches. Have you tries running Codegen/generic through your back end? That should give you some more test cases. Some "feature" tests can be found inside other directories as well, e.g. msp430 / systemz. Are you planning to add microblaze description to clang? C compiler can speed up testing alot :) More comments: >+SDValue MBlazeTargetLowering:: >+LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { Do you really need this? Expanding dynamic allocas normally ends with stack register adjustment, you don't need an...

Hi, i'm working on a microblaze port extremely similar to microblaze that only has data hazards. The advice given to look at PPC and ARM is poor because neither of them check for data dependencies and are entirely complicated and different. The port has a 5 stage pipeline where the result of instruction can only be used at s...

I have done some clean up on the MicroBlaze backend as requested by Anton Korobeynikov and Jakob Olesen. The new MicroBlaze backend patch is attached to this email. The patch is inclusive of the previous patch so you do not need to apply the previous patch before applying this patch. The new patch updated the following compared to the prev...

It has been a long time since I've been able to actually work with LLVM. It's good to be back. I know that the Microblaze code generator has been dropped due to the lack of a maintainer. I'm keeping it around in my source tree and will try to keep it current until it can be brought back into the LLVM fold. I finally tracked down a problem that has been bugging me for a while with the Microblaze version of the...

Sorry if this is a duplicate: I tried to send it last night and it didn't go through. I'm trimming some text to see if it helps. I have a simple program that fails on the Microblaze: int main() { unsigned long long x, y; x = 100; y = 0x8000000000000000ULL; return !(x > y); } As you can see, the test case compares two unsigned long long values. To try to track the problem down I tried compiling it for the Mips (which works, of course) for both unsig...

Hi guys, I'm new here. I want to write a backend for a microblaze clone, aemb. ( http://www.aeste.my/aemb). I already copy the existing Mblaze target and rename it into aemb and it work exactly as Mblaze, for now. My plan after this is to modify it according to my aemb core. The difference between aemb and MBlaze is that aemb support *two threads*. Any advise o...

...My goal is to target small embedded systems, but I think that what I'm working on may be of interest to other LLVM/clang developers as I have been able to use the environment to fix several code generation issues in LLVM. As of today, I can compile non-trivial programs for ARM, i386, Mips, Microblaze, PowerPC, PowerPC64, and X86_64. These programs can be run with the modified NetBSD C library under QEMU in Linux user space emulation mode on my X86_64 Linux box. If anyone is interested in trying it out it is at http://ellcc.org. Some important notes: * I have built this on a X86_64 Linux sy...

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0...

On 17 January 2011 10:30, Richard Pennington <rich at pennware.com> wrote: > * It is currently based on a fairly recent version of LLVM/clang: r122956. This is great. I've noticed that you've made some fixes or additions that haven't made it upstream yet, such as the Microblaze parameter fix in rev 2337 (CCed Wesley Peck as he seems to have done a lot of work on the MBlaze stack code recently) and va_arg support for Microblaze in rev 2350. Do you intend to push such fixes upstream? Regards, Alex

> -----Original Message----- > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: 08 July 2015 19:01 > To: Daniel Sanders > Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu); Eric Christopher > (echristo at gmail.com); Jim Grosbach (grosbach at apple.com) > Subject: Re: The Trouble with Triples > > On 8 July 2015 at 17:43, Daniel Sanders

...c 14, 2010, at 3:46 PM, Richard Pennington wrote: > Notice that the label $BB0_1 is missing. If I disable filling in the > branch delay slots, I get: Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and many other things have been updated for the Microblaze backend. In particular, the commit r120095 for the MBlaze backend fixed some issues with missing block labels due to AsmPrinter::isBlockOnlyReachableByFallthrough not taking into account delay slots in basic blocks. > My question is, why would inserting a NOP or splicing an instruction in &gt...

...however looking through the >> various files of the backend to try to find where the calling convention >> might be causing problems with f32 data types. > Form the backtrace it seems like you haven't defined how to return f32 > stuff out of the function. Could it be that the microblaze backend only has 2 return registers and we've written a function call that wants 3? If that could be the problem I'd guess it is highly likely because a lot of our code if 3 element vectors being passed around. Josef