llvm dev - Jul 2012 - [LLVMdev] Setting up a cross-compiler for cortex-m3

On Wed, Jul 18, 2012 at 6:08 PM, salvatore benedetto
<salvatore.benedetto at gmail.com> wrote:
> On Wed, Jul 18, 2012 at 5:45 PM, Renato Golin <rengolin at
systemcall.org> wrote:
>> On 18 July 2012 15:46, salvatore benedetto
>> <salvatore.benedetto at gmail.com> wrote:
>>> $ clang++ -ccc-host-triple thumbv7m-none-gnueabi noInclude.cpp -c
>>>
--sysroot=/home/emitrax/CodeSourcery/Sourcery_G++_Lite/arm-none-linux-gnueabi/libc/
>>
>> Try -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple
>> thumbv7m-none-linux-gnueabi
>>
>> Sometimes it's better than sysroot, as it finds it all by itself.
>
> And the winner is..
>
> clang++ -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple
> thumbv7m-none-gnueabi testReference.cpp -c
>
> It seems like it worked.
>
> $ arm-none-linux-gnueabi-objdump -D --section=.text testReference.o
>
> testReference.o:     file format elf32-littlearm
>
>
> Disassembly of section .text:
>
> 00000000 <main>:
>    0:   e92d4800        push    {fp, lr}
>    4:   e1a0b00d        mov     fp, sp
>    8:   e24dd030        sub     sp, sp, #48     ; 0x30
> ...
>
> I'm not 100% sure if that's the correct ISA, because I haven't
run the
> code, but it seems ok.
>
Unfortunately, I have to resurrect this thread.

I had the time to test the code, and it is using the wrong ISA.
I can't understand why, but it uses armv5te instead of thumb2.

$ clang++ -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple
thumbv7m-none-gnueabi testReference.cpp -c
$ arm-none-linux-gnueabi-readelf -A testReference.o
Attribute Section: aeabi
File Attributes
  Tag_CPU_name: "5TE"
  Tag_CPU_arch: v5TE
  Tag_ARM_ISA_use: Yes
  Tag_THUMB_ISA_use: Thumb-1
  Tag_ABI_FP_denormal: Needed
  Tag_ABI_FP_exceptions: Needed
  Tag_ABI_FP_number_model: IEEE 754
  Tag_ABI_align_needed: 8-byte
  Tag_ABI_align_preserved: 8-byte, except leaf SP
  Tag_DIV_use: Not allowed

I realized this only when I moved to compile my firmware and
got the following

/tmp/startup-EFUAJp.s: Assembler messages:
/tmp/startup-EFUAJp.s:84: Error: width suffixes are invalid in ARM
mode -- `ldr.w sp,[r0]'

Using the -v options produce the following

gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-57)
COLLECT_GCC_OPTIONS='-ffunction-sections' '-fno-common'
'-fno-exceptions' '-fno-rtti' '-v' '-nostdlib'
'-nodefaultlibs'
'-Wall' '-stdlib=libc++' '-I'
'/home/emitrax/bin/llvm/lib/c++/v1'
'-std=c++11' '-I'
'/home/emitrax/programming/adok/build/include/private' '-I'
'/home/emitrax/programming/adok/include/private' '-c'
'-o'
'source/porting/arch/arm/cortex-m3/stack.cpp.o' '-shared-libgcc'
'-march=armv5te' '-mtls-dialect=gnu' '-D'
'__CS_SOURCERYGXX_MAJ__=2012' '-D'
'__CS_SOURCERYGXX_MIN__=3' '-D'
'__CS_SOURCERYGXX_REV__=57'

Any suggestions?

Regards,
S.

> Any suggestions?
Try to specify CPU explicitly.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

On Sun, Jul 22, 2012 at 9:42 PM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
>> Any suggestions?
> Try to specify CPU explicitly.
Already did.

clang++ -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple
thumbv7m-none-gnueabi testReference.cpp -c -mcpu=cortex-m3
fatal error: error in backend: CPU: 'cortex-m3' does not support ARM
mode execution!

S.

On 22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info>
wrote:
>> Any suggestions?
> Try to specify CPU explicitly.
He shouldn't have to, but that might help. Maybe setting -march? This
is a big mess...

I thought that v7 always assumed Thumb2 for the thumb flag, and v7M
should always assume Cortex-M3 CPU if none provided.

It's funny that James had a great patch to solve all those problems by
implementing Clang's architecture selection in table-gen more than an
year ago. I wonder what happened to that thread... :/

-- 
cheers,
--renato

http://systemcall.org/