search for: mthumb

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2018 Nov 15
3
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...gt; > when I noticed that -Os gives me Thumb on Cortex-A{8,9,17} > > > I wanted to say: > > > when I noticed that "GCC -Os" gives me Thumb on Cortex-A{8,9,17} > > Yes. Just to clarify my response. That particular linaro toolchain (I've got 5.3) defaults to -mthumb. It will also give you thumb code if you compile with -O3 though. It is a toolchain default and not an implication of -Os or -Oz. My vote is not imply ARM/Thumb state changes with optimization options. We've already got two ways to do it --target=thumb-none-eabi, --target=arm-none-eabi and -mt...
2018 Nov 15
2
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...st having a play with this native compiler: gcc-5 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.10) 5.4.0 20160609 when I noticed that -Os gives me Thumb on Cortex-A{8,9,17}, which is what I would expect, but with Clang -Oz I get A32. I haven't thought about the implementation yet, but I hope passing -mthumb in the driver is not that difficult when we i) target an A-core and AArch32 state, and ii) we optimise for minimum size. And if I have to update a lot of tests, then that's what it is I am afraid, if we agree this is a sensible change that is. Cheers, Sjoerd. ____________________________...
2018 Nov 15
2
[RFC][ARM] -Oz implies -mthumb
...mmand line options and compiling for minimum code size, and wanted to check if there would be any problems or objections to my change. The problem is that compiling for minimum code size like this: -Oz --target=arm-arm--eabi -mcpu=cortex-xyz does not really give minimum code size because -mthumb is not enabled. This looks like a sub-optimal user experience to me, and also, it is inconsistent with GCC's behaviour. In other words: for AArch32, optimisation level -Oz targets A32, but I would like to change that to T32, and so I would like to propose that -Oz implies -mthumb. Cheers,...
2018 Nov 15
2
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
My understanding is that whether a gcc toolchain defaults to ARM or Thumb is a configuration time decision by whomever builds the toolchain. The linaro arm-linux-gnueabihf toolchain I have defaults to -mthumb and that doesn't vary for -mcpu or any other command line option. I haven't got a gcc to hand that defaults to -marm so that I can test whether -mcpu=cortex-m3 will change that to Thumb. If I try -marm -mcpu=cortex-m3 I get "error: target CPU does not support ARM mode". Can you g...
2018 Nov 15
3
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...r around. On Thu, Nov 15, 2018 at 4:14 AM, Tim Northover via cfe-dev < cfe-dev at lists.llvm.org> wrote: > Hi Sjoerd, > > On Thu, 15 Nov 2018 at 11:49, Sjoerd Meijer via cfe-dev > <cfe-dev at lists.llvm.org> wrote: > > does not really give minimum code size because -mthumb is not enabled. > This looks like a sub-optimal user experience to me, and also, it is > inconsistent with GCC's behaviour. > > Which version? None of the GCCs on Godbolt exhibit the kind of > switching you're describing as far as I can tell. > > Cheers. > > Tim....
2010 Jan 10
1
[LLVMdev] building a llvm-arm-elf crosscompiler on OSX 10.5
Dear ML, Anton, Thank you for your answer and your help. I had a look at ARM.td of LLVM 2.6 (in lib/Target/ARM..) where I found following definitions: // V4T Processors. def : ProcNoItin<"arm7tdmi", [ArchV4T]>; def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; def : ProcNoItin<"arm710t", [ArchV4T]>; def :
2018 Nov 08
2
Compile with both arm and thumb mode
Hi I would like to use clang to cross compile the ARM binary. I hope the target binary contains both arm and thumb instruction sets. I use the flag -mhwdiv=arm,thumb. I compiled several binaries. However, I found that the thumb mode instructions are few. Even for very big program like gcc. The number of thumb mode instruction is less than 100. I get the ground truth from the mapping table.
2012 Jul 22
2
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Sun, Jul 22, 2012 at 9:42 PM, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> Any suggestions? > Try to specify CPU explicitly. Already did. clang++ -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple thumbv7m-none-gnueabi testReference.cpp -c -mcpu=cortex-m3 fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode execution! S.
2012 Jul 22
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
> clang++ -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple > thumbv7m-none-gnueabi testReference.cpp -c -mcpu=cortex-m3 > fatal error: error in backend: CPU: 'cortex-m3' does not support ARM > mode execution! Ok, and what's about -mthumb then? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
2013 Oct 12
2
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
On 12 October 2013 23:00, Amara Emerson <amara.emerson at gmail.com> wrote: > Hi Jan, > > For Cortex-M0, you should probably use the armv6m string in the target > triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb > won't be necessary. > Yes, but I agree with Jim that a bug must be filled. Jan, would you mind filling a bug? http://llvm.org/bugs/enter_bug.cgi?product=clang cheers, --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/p...
2012 Aug 16
0
[LLVMdev] error: instruction requires: thumb2
...nerated. > ------------------------------------------------------- > > In the main.c, some ARM assembly are embedded which contains instructions ldrex, strexeq. I don't know what the message suggests since the cpu specified does support thumb2. Could someone help? Thanks. Try "-mthumb". -Eli
2020 Apr 15
2
[ARM] Register pressure with -mthumb forces register reload before each call
..._______________ > From: Prathamesh Kulkarni <prathamesh.kulkarni at linaro.org> > Sent: 15 April 2020 01:44 > To: John Brawn <John.Brawn at arm.com> > Cc: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> > Subject: Re: [llvm-dev] [ARM] Register pressure with -mthumb forces register reload before each call > > Hi, > I have attached WIP patch for adding foldMemoryOperand to Thumb1InstrInfo. > For the following case: > > void f(int x, int y, int z) > { > void bar(int, int, int); > > bar(x, y, z); > bar(x, z, y); > bar(y...
2013 Oct 11
3
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
Hi, I am trying to cross compile code for ARM Cortex m0, m3, and m4. For m0, I use: -target armv6--eabi -mcpu=cortex-m0 That seems to work. For m3 and m4, I use the following which does not work (fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode): -target armv7m--eabi -mcpu=cortex-m3 and -target armv7em--eabi -mcpu=cortex-m4 Who can help me with the
2012 Aug 16
3
[LLVMdev] error: instruction requires: thumb2
Hi Everybody, I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c and get error message: ------------------------------------------------------- main.c:9:9: error: instruction requires: thumb2 "ldrex
2012 Aug 16
2
[LLVMdev] error: instruction requires: thumb2
...--------------------------------------------------- >> >> In the main.c, some ARM assembly are embedded which contains instructions ldrex, strexeq. I don't know what the message suggests since the cpu specified does support thumb2. Could someone help? Thanks. > > Try "-mthumb". > > -Eli
2016 May 18
2
LLVM issuse:AArch64 TargetParser
Hi, A64 versus A32/T32 code generation is controlled by the -target option which I don’t believe is under discussion here. James On 18 May 2016, at 13:17, Bruce Hoult <bruce at hoult.org<mailto:bruce at hoult.org>> wrote: Note that armv8a modifies the A32 and T32 instruction sets, and is therefore an important -march option for 32 bit code. Therefore armv8a can not be used to imply
2013 Oct 12
0
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
Hi Jan, For Cortex-M0, you should probably use the armv6m string in the target triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb won't be necessary. Amara On 11 October 2013 19:23, Jan Hoogerbrugge < jan.hoogerbrugge at biface-tools.com> wrote: > Hi, > > I am trying to cross compile code for ARM Cortex m0, m3, and m4. > > For m0, I use: > > -target armv6--eabi -mcpu=cortex-m0 > > Th...
2013 Oct 14
0
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
...rson at gmail.com<javascript:_e({}, 'cvml', 'amara.emerson at gmail.com');> > > wrote: > >> Hi Jan, >> >> For Cortex-M0, you should probably use the armv6m string in the target >> triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb >> won't be necessary. >> > > Yes, but I agree with Jim that a bug must be filled. > > Jan, would you mind filling a bug? > > http://llvm.org/bugs/enter_bug.cgi?product=clang > > cheers, > --renato > -------------- next part -------------- An HTML attac...
2013 Oct 14
1
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
...gt; >> On 12 October 2013 23:00, Amara Emerson <amara.emerson at gmail.com> wrote: >> >>> Hi Jan, >>> >>> For Cortex-M0, you should probably use the armv6m string in the target >>> triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb >>> won't be necessary. >>> >> >> Yes, but I agree with Jim that a bug must be filled. >> >> Jan, would you mind filling a bug? >> >> http://llvm.org/bugs/enter_bug.cgi?product=clang >> >> cheers, >> --renato >> >...
2012 Dec 08
2
[LLVMdev] Compile code for arm
...inary. Can anyone help me what are the steps > which > > should I take? > > clang -triple arm-none-eabi (or many other variations including > 'armv5', 'armv7a', 'linux', 'gnueabi', etc). > > There are other options, like -mcpu, -mfpu, -march, -mthumb that you > can also tune. I'm not sure there is a list of all available options, > but since you have the source, you can look into ToolChain.cpp or > Tools.cpp in Clang/lib/Driver and see for yourself all the available > options. > > > > Second question, Is there anyway...