Sebastien DELDON-GNB
2012-Jun-25 13:46 UTC
[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?
Hi Anton, You're right it fails with a different message with llc 3.0. Anyway thanks for your help. Best Regards Seb> -----Original Message----- > From: Anton Korobeynikov [mailto:anton at korobeynikov.info] > Sent: Monday, June 25, 2012 3:39 PM > To: Sebastien DELDON-GNB > Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav > Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9 + neon ? > > > I filled this problem a while ago here > http://llvm.org/bugs/show_bug.cgi?id=13111 > > Thinking it first was an LLVM opt bug. Shall I assign it to Nadav or > create a new one ? > IR is correct per se, so, backend should handle it (and it is w/o > vector promotion). Everything was ok, because vector promotion was > disabled by default on 3.0. > You may try to check with llc -promote-elements=1 on llc from 3.0. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University
Sebastien DELDON-GNB
2012-Jun-25 15:18 UTC
[LLVMdev] RE : RE : Is llc broken for Cortex-A9 + neon ?
Hi all, More on this topic, if I use llc 3.1 with -promote-elements=0 as follows: llc convect.llvm -march=arm -mcpu=cortex-a9 -promote-elements=0 -mattr=+neon,+neonfp -relocation-model=pic -o convect.s then it fails, whereas it compiles with promote elements set to 1, trace looks like: # In Register Scavenger # Machine code for function test_kernel: Post SSA Frame Objects: fi#-18: size=4, align=8, fixed, at location [SP+264] ... Function Live Ins: %R2 in %vreg1, %R3 in %vreg2 BB#0: derived from LLVM BB %L.entry Live Ins: %R2 %R3 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R11 %LR %D8 %D9 %D10 %D11 %D12 %D13 %D14 %D15 %SP<def> = STMDB_UPD %SP, pred:14, pred:%noreg, %R4<kill>, %R5<kill>, %R6<kill>, %R7<kill>, %R8<kill>, %R9<kill>, %R10<kill>, %R11<kill>, %LR<kill>; flags: FrameSetup %SP<def> = VSTMDDB_UPD %SP, pred:14, pred:%noreg, %D8<kill>, %D9<kill>, %D10<kill>, %D11<kill>, %D12<kill>, %D13<kill>, %D14<kill>, %D15<kill>; flags: FrameSetup ... %SP<def> = LDMIA_RET %SP, pred:14, pred:%noreg, %R4<def>, %R5<def>, %R6<def>, %R7<def>, %R8<def>, %R9<def>, %R10<def>, %R11<def>, %PC<def> # End machine code for function test_kernel. *** Bad machine code: Using an undefined physical register *** - function: test_kernel - basic block: L.entry 0x1f65870 (BB#0) - instruction: %S17<def> = VMOVSR %R0<kill>, pred:14, pred:%noreg, %D8<imp-def>, %Q4<imp-use,kill>, %Q4<imp-def> - operand 5: %Q4<imp-use,kill> LLVM ERROR: Found 1 machine code errors. ________________________________________ De : Sebastien DELDON-GNB Date d'envoi : lundi 25 juin 2012 15:46 À : Anton Korobeynikov Cc : LLVMdev at cs.uiuc.edu; Rotem, Nadav; Sebastien DELDON-GNB Objet : RE: RE : [LLVMdev] Is llc broken for Cortex-A9 + neon ? Hi Anton, You're right it fails with a different message with llc 3.0. Anyway thanks for your help. Best Regards Seb> -----Original Message----- > From: Anton Korobeynikov [mailto:anton at korobeynikov.info] > Sent: Monday, June 25, 2012 3:39 PM > To: Sebastien DELDON-GNB > Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav > Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9 + neon ? > > > I filled this problem a while ago here > http://llvm.org/bugs/show_bug.cgi?id=13111 > > Thinking it first was an LLVM opt bug. Shall I assign it to Nadav or > create a new one ? > IR is correct per se, so, backend should handle it (and it is w/o > vector promotion). Everything was ok, because vector promotion was > disabled by default on 3.0. > You may try to check with llc -promote-elements=1 on llc from 3.0. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University
Anton Korobeynikov
2012-Jun-25 15:28 UTC
[LLVMdev] RE : RE : Is llc broken for Cortex-A9 + neon ?
> llc convect.llvm -march=arm -mcpu=cortex-a9 -promote-elements=0 -mattr=+neon,+neonfp -relocation-model=pic -o convect.sSomething is weird, it should not run machine code verifier here... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University