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I'm running 1.0-test49 on Solaris 2.8. The good news is that this version fixes my problem with corrupted index files (so far). The bad news is it seems to be leaking FDs to do with inbox: imap 10198 gnb 156r VDIR 255,7032 8192 5784160 /home/gnb/Maildir/new imap 10198 gnb 157r VDIR 255,7032 1093632 2917923 /home/gnb/Maildir/cur imap 10198 gnb 158r VDIR 255,7032 8192 5784160 /home/gnb/Maildir/new imap 10198 gnb 159r VDIR 255,7032 1093632 2917923...

...A9 support it but isn't documented/recommended ? And as mentioned before code is working ! Seb > -----Original Message----- > From: rengolin at gmail.com [mailto:rengolin at gmail.com] On Behalf Of > Renato Golin > Sent: Friday, November 09, 2012 6:27 PM > To: Sebastien DELDON-GNB > Cc: JF Bastien; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] fmac generation for cortex-a9 > > Hi Sebastien, > > ARMv7-M has VFMA and LLVM's "triple" is far from perfect. > > Wikipedia tells me NovaThor can also be A15, or STE could have cramped a >...

cat /proc/cpuinfo ? Are you sure it's generating VFMA and not VMLA? On Fri, Nov 9, 2012 at 9:35 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Renato, > > It's definitively not A15. Can this be the case that NEON units for > cortex-A9 support it but isn't documented/recommended ? > And as mentioned before code is working ! > > Seb > > > > -----Origin...

...for my platform STEricsson Novathor with Linaro, code works. It also works when I use LLVM to generate fma (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer the question ? Seb From: JF Bastien [mailto:jfb at google.com] Sent: Friday, November 09, 2012 5:36 PM To: Sebastien DELDON-GNB Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] fmac generation for cortex-a9 AFAIK A9 doesn't have VFPv4 or AdvSIMDv2, so it doesn't have VFMA. I don't know what LLVM does, but it shouldn't emit VFMA when you target A9. VMLA isn't a fused multiply-add, it...

...erfect. Wikipedia tells me NovaThor can also be A15, or STE could have cramped a VFPv4 in it? ;) Or possibly, your code never branches into the VFMA. Many things could be happening, but usually, VFMA shouldn't be generated for A9. A GCC bug, maybe? On 9 November 2012 16:51, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > Hi Bastien, > > > > Weird gcc is generating fma for my platform STEricsson Novathor with Linaro, > code works. It also works when I use LLVM to generate fma (using llc > –mtriple=armv7-eabi). Maybe someone from ARM can answer the ques...

...se an exception (SEGFAULT), I just want to know if there is a way to enforce generation of movupd instruction instead of movapd. Seb > -----Original Message----- > From: David A. Greene [mailto:greened at obbligato.org] > Sent: Friday, February 25, 2011 5:13 PM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Use of movupd instead of movapd for x86 > > Sebastien DELDON-GNB <sebastien.deldon at st.com> writes: > > > Hi all, > > > > Is there a way to force llc to generate movupd instruction instead of > movap...

Hi, I have recently installed R in my Linux(Red Hat 5.1) box without any problems. At the time I run some plots or demos, like the "demo(image)" I get the following error: "Error: color allocation error" Do you what's going wrong with the colors? Best, Georgios. -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.- r-help mailing list -- Read

...ack to the original problem why when using -mcpu=cortex-a9 VMLA/VMLS are not generated and when I use -mtriple=armv7-eabi they are ? Best Regards Seb ________________________________________ De : JF Bastien [jfb at google.com] Date d'envoi : vendredi 9 novembre 2012 18:45 À : Sebastien DELDON-GNB Cc : Renato Golin; llvmdev at cs.uiuc.edu Objet : Re: [LLVMdev] fmac generation for cortex-a9 cat /proc/cpuinfo ? Are you sure it's generating VFMA and not VMLA? On Fri, Nov 9, 2012 at 9:35 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com<mailto:sebastien.deldon at st.com>>...

...ion for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com] > Sent: Thursday, November 08, 2012 10:22 AM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] fmac generation for cortex-a9 > > On 8 November 2012 13:56, Sebastien DELDON-GNB > <sebastien.deldon at st.com> wrote: > > Hi all, > > > > > > > > > > > > I've a .ll code that u...

On Feb 28, 2011, at 2:58 AM, Sebastien DELDON-GNB wrote: > Understood for the aligned case, I want to measure performance degradation for unaligned case. > I mean unaligned case versus aligned. I know this is stupid, but I want to try to pass a <4 x float>* as parameter of a routine and at the call site I want to pass a misaligned poi...

...AdvSIMDv2, so it doesn't have VFMA. I don't know what LLVM does, but it shouldn't emit VFMA when you target A9. VMLA isn't a fused multiply-add, it's a multiply followed by an add and has different latency as well as precision. On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Anitha, > > Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable > fused mac generation for me. > I would like just to understand why -mtriple=armv7-eabi enables it while > -mcpu=cortex-a9 seems to disable it...

...e answer, for Cortex-A9 would you recommend to generate thumb2 code or ARM code ? What would be the best performance wise ? Best Regards Seb > -----Original Message----- > From: James Molloy [mailto:james.molloy at arm.com] > Sent: Thursday, May 31, 2012 9:57 AM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] llc support for ARM predication ? > > Hi Seb, > > The ARM instruction set is a fixed-width 32-bit instruction set that > has > been around since the early days of ARM. > > Modern (armv4t onwards) cores mostly hav...

...could be adapted to 'legalize' intrinsics calls ? Or shall I define my own intrinsics for non supported types ? Best Regards Seb ________________________________________ De : Eli Friedman [eli.friedman at gmail.com] Date d'envoi : vendredi 21 septembre 2012 11:54 À : Sebastien DELDON-GNB Cc : llvmdev at cs.uiuc.edu Objet : Re: [LLVMdev] Question about LLVM NEON intrinsics On Fri, Sep 21, 2012 at 1:28 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > Hi all, > > I would like to know if LLVM Neon intrinsics are designed to support only 'Legal' typ...

On Sep 21, 2012, at 2:58 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > Hi Eli, > > Thanks for the answer, it clarifies the situation for me. Do you know if there is Pass in LLVM that could be adapted to 'legalize' intrinsics calls ? > Or shall I define my own intrinsics for non supported types ? You s...

Hi all, Is there a way to force llc to generate movupd instruction instead of movapd for x86 target ? I know that movapd is more performant, but I would like to measure degradation when alignment constraints are not met. Best Regards Seb -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 12 February 2013 16:56, Sebastien DELDON-GNB <sebastien.deldon at st.com>wrote: > If this helps taking your decision, there are at least two benchmarks for > which disabling vmlx-forwarding makes a significant difference. > I think Evan's worry was to base this decision on visible and comprehensible benchmarks, such as th...

...---- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of James Molloy > Sent: Tuesday, May 29, 2012 5:38 PM > To: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] llc support for ARM predication ? > > On 29/05/12 15:39, Sebastien DELDON-GNB wrote: > > Hi all, > > > > I was wondering if 'llc' is able to generate 'it' instruction for ARM > Cortex-A9 target ? > > > > Thanks for your answers > > Seb > > > > _______________________________________________ > > LLVM Dev...

Hi Rotem, Thanks for the quick answer, how do I know which type is legal/illegal with respect to calling convention ? Best Regards Seb > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Thursday, July 05, 2012 11:21 AM > To: Sebastien DELDON-GNB; llvmdev at cs.uiuc.edu > Subject: RE: Vector argument passing abi for ARM ? > > The argument passing calling convention is undefined for illegal types, > such as <2 x i8>. The invalid misaligned loads on ARM sounds like a bug > in the ARM backend. > > -----Original Mes...

...n v6t2. v7 includes Thumb-2 by default (for A-class cores such as Cortex-A8). So when specifying "thumbv7" as the architecture to LLVM, LLVM will generate Thumb-2 instructions and use IT instructions for conditional execution. Hope this helps, James On 30/05/12 23:34, Sebastien DELDON-GNB wrote: > Hi James, > > Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7. > I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ? > > Best Regards > Seb > >> -----Original Message-...

...my front-end to generate llvm neon intrinsics that maps to LLVM vmla/vmls f32 when I think it is appropriate and not to rely on disabling/enabling vmlx-forwarding. Best Regards Seb From: Renato Golin [mailto:renato.golin at linaro.org] Sent: Friday, February 08, 2013 11:54 AM To: Sebastien DELDON-GNB Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Is there any llvm neon intrinsic that maps to vmla.f32 instruction ? On 8 February 2013 10:40, Sebastien DELDON-GNB <sebastien.deldon at st.com<mailto:sebastien.deldon at st.com>> wrote: Hi all, Everything is in the tile, I would like...