llvm dev - Mar 2012 - [LLVMdev] VLIWPacketizerList: failing to schedule terminators

Hi Tom,

We also ran into the same issue when packetizing for Hexagon. Let me try to
explain the problem:

The scheduler breaks down a basic block into regions (look at
MachineScheduler.cpp) - I believe for efficiency. There is an API
isSchedulingBoundary to check if an instruction is a scheduling boundary or
not. If it is a scheduling boundary, all existing instructions in the region
are scheduled and next region is started.

By default, isSchedulingBoundary returns true for labels and terminator
instructions. Further, there is a check in BuildSchedGraph (I think) that
asserts if it finds labels or terminator. I think that assert should be
changed to use isSchedulingBoundary API.

Another problem for VLIW machines is packetization of terminator instruction
with other instructions. For example, Hexagon allows to packetize
terminators with others if there is no true dependence. In the current
infrastructure, it's not possible to allow terminators to be included in the
region since it will assert in BuildSchedGraph.

I propose the following solution:

1. Change assert in BuildSchedGraph to use isSchedulingBoundary.
2. Change DAG construction so that there is a control edge between every
leaf node to the terminator instruction.
3. VLIW backends, override isSchedulingBoundary to return false for
terminators; 4. The region formation algorithm will select the entire basic
block (if there are no labels) for scheduling including terminators.
5. Control edge will make sure that terminator instruction is not reordered.

Please let me know what you guys think.

Thanks,
Sundeep
> -----Original Message-----
> From: Das Gupta, Anshu
> Sent: Thursday, March 29, 2012 1:46 PM
> To: sundeepk at codeauroraforum.org; Kushwaha, Sundeep
> Subject: FW: [LLVMdev] VLIWPacketizerList: failing to schedule terminators
> 
> 
> 
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Tom Stellard
> Sent: Thursday, March 29, 2012 11:01 AM
> To: Anshuman Dasgupta; Sergei Larin
> Cc: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] VLIWPacketizerList: failing to schedule terminators
> 
> Hi,
> 
> I'm trying to use the VLIWPacketizerList to schedule instructions for
the
R600
> target, and I'm running into this assertion failure:
> ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels!
> 
> I think I might not be using the VLIWPacketizerList class correctly.
> I've attached my code to this email.  Can anyone spot what I'm
doing
wrong?
> 
> Also, I had to add a LiveIntervals * parameter to the constructor of this
class
> in order to do pre-RA scheduling.
> 
> 
> Thanks,
> Tom