search for: vliwpacketizerlist

Hi, I'm trying to use the VLIWPacketizerList to schedule instructions for the R600 target, and I'm running into this assertion failure: ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels! I think I might not be using the VLIWPacketizerList class correctly. I've attached my code to this email. Can anyone spot what I'...

...ok like that function is ever called. -Tom > > -----Original Message----- > > From: Tom Stellard [mailto:thomas.stellard at amd.com] > > Sent: Thursday, March 29, 2012 11:01 AM > > To: Anshuman Dasgupta; Sergei Larin > > Cc: llvmdev at cs.uiuc.edu > > Subject: VLIWPacketizerList: failing to schedule terminators > > > > Hi, > > > > I'm trying to use the VLIWPacketizerList to schedule instructions for > > the R600 target, and I'm running into this assertion failure: > > ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or la...

...in -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: Tom Stellard [mailto:thomas.stellard at amd.com] > Sent: Thursday, March 29, 2012 11:01 AM > To: Anshuman Dasgupta; Sergei Larin > Cc: llvmdev at cs.uiuc.edu > Subject: VLIWPacketizerList: failing to schedule terminators > > Hi, > > I'm trying to use the VLIWPacketizerList to schedule instructions for > the R600 target, and I'm running into this assertion failure: > ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels! > > I think I mig...

...mm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: Tom Stellard [mailto:thomas.stellard at amd.com] > Sent: Thursday, March 29, 2012 2:23 PM > To: Sergei Larin > Cc: 'Anshuman Dasgupta'; llvmdev at cs.uiuc.edu > Subject: Re: VLIWPacketizerList: failing to schedule terminators > > On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > > Tom, > > > > What is in your isSchedulingBoundary? If it contains isLabel you > might > > need to disable that assert: > > > > assert(!MI->isTerm...

...re that terminator instruction is not reordered. Please let me know what you guys think. Thanks, Sundeep > -----Original Message----- > From: Das Gupta, Anshu > Sent: Thursday, March 29, 2012 1:46 PM > To: sundeepk at codeauroraforum.org; Kushwaha, Sundeep > Subject: FW: [LLVMdev] VLIWPacketizerList: failing to schedule terminators > > > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: Thursday, March 29, 2012 11:01 AM > To: Anshuman Dasgupta; Sergei Larin > Cc: llvmdev...

...f Code Aurora Forum. > > > > -----Original Message----- > > From: Tom Stellard [mailto:thomas.stellard at amd.com] > > Sent: Thursday, March 29, 2012 2:23 PM > > To: Sergei Larin > > Cc: 'Anshuman Dasgupta'; llvmdev at cs.uiuc.edu > > Subject: Re: VLIWPacketizerList: failing to schedule terminators > > > > On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > > > Tom, > > > > > > What is in your isSchedulingBoundary? If it contains isLabel you > > might > > > need to disable that assert: > &...

...t; > > -Tom > > > >> > >> Andy, > >> > >> Those are just my guesses, but the issue looks very similar to our first > >> experience with sched DAG constructor. > >> > >> Sergei > > Tom, > > The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. Ok, so I think I...

...get the program > to compile, and it has the VLIW bundles. > > -Tom > >> >> Andy, >> >> Those are just my guesses, but the issue looks very similar to our first >> experience with sched DAG constructor. >> >> Sergei Tom, The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. To me, the definit...

...n't > require a custom scheduler. Although I don't want to stop you from > generalizing the DFA work either if you feel compelled to do that. I don't yet feel compelled, and I don't know much about the DFAPacketizer. I just want something that will work cleanly ;) Looking at VLIWPacketizerList::PacketizeMIs, it seems like the instructions are first scheduled (via some external scheme?), and then packetized 'in order'. Is that correct? > > Ignoring compile time for a moment, I think an advantage of a DFA is > modeling a situation where the hardware can assign resources...

...rror and it crashes > out before packeting a single instruction. Do you reserve some resource without verification? Note that reserveResources() should be called iff canReserveResources() is true (the call order is important here) even for the trivial case (0 instructions in the packet). See VLIWPacketizerList as an example on how to use the API's. Ivan > > I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the > table is not empty before proceeding. I also have a schedule file with my > functional units and itineraries listed. Can anyone think of what I may have &g...

On Wed, Sep 05, 2012 at 07:48:48PM +0200, JUHASZ David wrote: > Hi, > > I would like to inform the community that I'm releasing the backend for > tile64 I developed in the past several months. It can be downloaded from > > http://pnyf.inf.elte.hu/juhda/projects/tilera/ > > The version for LLVM 3.1 is a minimalist functioning implementation. Now > I am working on

On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Looking at VLIWPacketizerList::PacketizeMIs, it seems like the > instructions are first scheduled (via some external scheme?), and then > packetized 'in order'. Is that correct? Anshu? > In the PowerPC grouping scheme, resources are assigned on a group > basis (by the instruction dispatching stages). Howe...

Hi, I'm trying to get the DFAPacketizer to work for my target but with any instruction I get the 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes out before packeting a single instruction. I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the table is not empty before proceeding. I also have a schedule file with my functional

Hi, I would like to inform the community that I'm releasing the backend for tile64 I developed in the past several months. It can be downloaded from http://pnyf.inf.elte.hu/juhda/projects/tilera/ The version for LLVM 3.1 is a minimalist functioning implementation. Now I am working on utilizing the VLIW packetizer of LLVM, and other improvements are planned for the future. I would be

...ut before packeting a single instruction. > > Do you reserve some resource without verification? > > Note that reserveResources() should be called iff canReserveResources() > is true (the call order is important here) even for the trivial case (0 > instructions in the packet). See VLIWPacketizerList as an example on how > to use the API's. > > Ivan > > > > > I have a *GenDFAPacketizer.inc file and my packetizer pass checks > that the > > table is not empty before proceeding. I also have a schedule file > with my > > functional units and itinerari...

...'m trying to figure out how Hexagon (I'm using it as an example for my own VLIW) is handling bundles with 1 instruction, but I don't quite get it. Here is the code that I have for a endPacket // endPacket - End the current packet, bundle packet instructions and reset // DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) { if (CurrentPacketMIs.size() > 1) { MachineInstr *MIFirst = CurrentPacketMIs.front(); finalizeBundle(*MBB, MIFirst, MI); } CurrentPacketMIs.clear(); ResourceTracker->clearResources()...

Is there a way to place a bundle a BUNDLE instruction into a packet with one instruction? Current code to end packet doesn't handle this case: // endPacket - End the current packet, bundle packet instructions and reset // DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) { if (CurrentPacketMIs.size() > 1) { MachineInstr *MIFirst = CurrentPacketMIs.front(); finalizeBundle(*MBB, MIFirst, MI); } CurrentPacketMIs.clear(); ResourceTracker->clearResources()...

...ngle instruction. >> >> Do you reserve some resource without verification? >> >> Note that reserveResources() should be called iff canReserveResources() >> is true (the call order is important here) even for the trivial case (0 >> instructions in the packet). See VLIWPacketizerList as an example on how >> to use the API's. >> >> Ivan >> >> > >> > I have a *GenDFAPacketizer.inc file and my packetizer pass checks >> that the >> > table is not empty before proceeding. I also have a schedule file >> with my >...

On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > I'm considering writing more-detailed itineraries for some PowerPC CPUs > that use the 'traditional' instruction grouping scheme. In essence, > this means that multiple instructions will stall in some pipeline stage > until a complete group is formed, then all will continue. > > I expect to

I'm considering writing more-detailed itineraries for some PowerPC CPUs that use the 'traditional' instruction grouping scheme. In essence, this means that multiple instructions will stall in some pipeline stage until a complete group is formed, then all will continue. I expect to provide CPU-specific code to help determine when the currently-waiting instructions would form a group.