search for: isschedulingboundary

...call stack, but packetizer calls > ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is > the first time you use the new MI sched infrastructure (like your target has > not implemented misched yet) there might be some work needed to implement > couple target hooks. isSchedulingBoundary is one of them. Also try to > disable that assert and see what happens. It sounds strange, but in some > cases that assert is overly restrictive. Thanks, I disabled that assert, and I got a little farther. I hit some more assertion failures finalizeBundle, because the instructions were stil...

...packetizer calls >> ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is >> the first time you use the new MI sched infrastructure (like your target has >> not implemented misched yet) there might be some work needed to implement >> couple target hooks. isSchedulingBoundary is one of them. Also try to >> disable that assert and see what happens. It sounds strange, but in some >> cases that assert is overly restrictive. > > Thanks, I disabled that assert, and I got a little farther. I hit > some more assertion failures finalizeBundle, because the...

Hi Tom, We also ran into the same issue when packetizing for Hexagon. Let me try to explain the problem: The scheduler breaks down a basic block into regions (look at MachineScheduler.cpp) - I believe for efficiency. There is an API isSchedulingBoundary to check if an instruction is a scheduling boundary or not. If it is a scheduling boundary, all existing instructions in the region are scheduled and next region is started. By default, isSchedulingBoundary returns true for labels and terminator instructions. Further, there is a check in BuildSche...

I found myself wanting a "scheduling barrier" in LLVM. In my specific circumstances I only want it to mean that TargetInstrInfoImpl::isSchedulingBoundary() would return true. I added SchedulingBarrier to MCID in MCInstrDesc.h and pushed it through TD attributes down to isSchedulingBoundary(). Is this something of general interest, or is there another mechanism for implementing barriers that I missed? Thanks -------------- next part ------------...

Hi Tim, Thank you a lot for your reply. So IIUC, optimization passes in opt do not reorder IR instructions, only passes in llc that move MIR instructions around. Is it correct? On the back-end (llc) side, hasSideEffects might prevent some reordering. But I just learn about TargetInstrInfo::isSchedulingBoundary. Can you tell me what are the differences between the two please? Thank you very much (again), Son Tuan Vu On Mon, Sep 17, 2018 at 12:13 PM Tim Northover <t.p.northover at gmail.com> wrote: > Hi, > > On Sun, 16 Sep 2018 at 22:02, Son Tuan VU via llvm-dev > <llvm-dev at lis...

...t; >> ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is > >> the first time you use the new MI sched infrastructure (like your target has > >> not implemented misched yet) there might be some work needed to implement > >> couple target hooks. isSchedulingBoundary is one of them. Also try to > >> disable that assert and see what happens. It sounds strange, but in some > >> cases that assert is overly restrictive. > > > > Thanks, I disabled that assert, and I got a little farther. I hit > > some more assertion failures fi...

On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > Tom, > > What is in your isSchedulingBoundary? If it contains isLabel you might > need to disable that assert: > > assert(!MI->isTerminator() && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > > Sergei Larin > > -- > Qualcomm Innovation Center, Inc. is a...

...I do not have your call stack, but packetizer calls ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is the first time you use the new MI sched infrastructure (like your target has not implemented misched yet) there might be some work needed to implement couple target hooks. isSchedulingBoundary is one of them. Also try to disable that assert and see what happens. It sounds strange, but in some cases that assert is overly restrictive. Andy, Those are just my guesses, but the issue looks very similar to our first experience with sched DAG constructor. Sergei -- Qualcomm Innovation Ce...

Tom, What is in your isSchedulingBoundary? If it contains isLabel you might need to disable that assert: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Orig...

Hi, I would like to access the AsmPrinter MachineFunctionPass during compilation in order to do alternative dumping of instructions, instead of using MI->dump(), which can get a bit messy. Is there any way to access this object or the assembler strings? It seems that even these strings / methods are not available through any static methods. Does it exist during the whole compilation or is it

...have discovered a case where it seems very far from 'strict'. I had two MI's, A and B, where A is !isSafeToMove(): A B TwoAddress pass changes the order to B A , as it reschedules the LastKill MI (B). Is this a bug in TwoAdress, or is it the case that isSafeToMove() is weaker than isSchedulingBoundary() so that these indirect violations are expected and accepted in TwoAddress and elsewhere? Thanks, Jonas

...the MI as isTerminator should have the same impact, yes? I'm not sure of the other consequences of this though, if any, have to look into it. Thanks. -Ryan On Tue, Nov 15, 2016 at 5:18 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > You can override TargetInstrInfo::isSchedulingBoundary for that. > > -Krzysztof > > On 11/15/2016 4:13 PM, Ryan Taylor wrote: > >> I have the same issue, would it be easier and more useful to attach a >> flag to the instruction to tell the scheduler not to move instructions >> across this boundary? >> >> -Ry...

Hi, I'm trying to use the VLIWPacketizerList to schedule instructions for the R600 target, and I'm running into this assertion failure: ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels! I think I might not be using the VLIWPacketizerList class correctly. I've attached my code to this email. Can anyone spot what I'm doing wrong? Also, I had to add a LiveIntervals

...ound > any other? Does the instruction have isSideEffects set on it? Where can I find information about isSideEffects? Googling "LLVm isSideEffects" didnt' reveal anything that looked relevant. > I think the fallback if that isn’t enough is to override TargetInstrInfo:: > isSchedulingBoundary > > Thanks, I'll look at that in other targets. Phil > -Matt -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160822/e81147cf/attachment-0001.html>

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT: fence 2 %foo.addr = alloca i32, align 4 store i32 %foo,

I have the same issue, would it be easier and more useful to attach a flag to the instruction to tell the scheduler not to move instructions across this boundary? -Ryan On Tue, Nov 15, 2016 at 5:11 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > You can create a DAG mutation that adds artificial dependencies between A, > B and Z. > > -Krzysztof >

Hello all, I want to add a custom intrinsic to the LLVM IR which would be lowered into a pseudo instruction since it doesn't correspond to any real instruction defined by the architecture. The speciality of this intrinsic/pseudo instruction that it should behave like a scheduling barrier: every instruction before the intrinsic has to be emitted before the intrinsic, the same goes for all

...uction - ignore pseudo instructions. >> -bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI, >> - MachineBasicBlock *MBB) { >> - if (MI->isDebugValue()) >> - return true; >> - >> - if (TII->isSchedulingBoundary(MI, MBB, MF)) >> - return true; >> - >> - return false; >> -} >> - >> -// isSoloInstruction - return true if instruction I must end previous >> -// packet. >> -bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) { >> - if (I->isI...