Heikki Kultala
2012-Mar-05 13:39 UTC
[LLVMdev] commit r152019 broke architectures with more than 255 registers
Our architecture(TCE) can have LOTS of registers. It seems r152019 changed some register bookkeeping data structures to 8-bit. This broke support for architectures with >255 registers. Please revert this change or make those register-related values at least 16 bits wide.
Villmow, Micah
2012-Mar-05 17:36 UTC
[LLVMdev] commit r152019 broke architectures with more than 255 registers
Ughh... yeah I would have to agree here. The AMDIL backend uses more than 256 registers to model its register file correctly.> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Heikki Kultala > Sent: Monday, March 05, 2012 5:39 AM > To: LLVM Dev > Subject: [LLVMdev] commit r152019 broke architectures with more than > 255 registers > > Our architecture(TCE) can have LOTS of registers. > > It seems r152019 changed some register bookkeeping data structures to > 8-bit. This broke support for architectures with >255 registers. > > Please revert this change or make those register-related values at > least > 16 bits wide. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Jakob Stoklund Olesen
2012-Mar-05 18:40 UTC
[LLVMdev] commit r152019 broke architectures with more than 255 registers
On Mar 5, 2012, at 5:39 AM, Heikki Kultala wrote:> Our architecture(TCE) can have LOTS of registers. > > It seems r152019 changed some register bookkeeping data structures to > 8-bit. This broke support for architectures with >255 registers. > > Please revert this change or make those register-related values at least > 16 bits wide.I agree. We can limit the number of physregs to 64k, but no more. /jakob
Craig Topper
2012-Mar-06 08:33 UTC
[LLVMdev] commit r152019 broke architectures with more than 255 registers
This has been changed to uint16_t in r152100. On Mon, Mar 5, 2012 at 10:40 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:> > On Mar 5, 2012, at 5:39 AM, Heikki Kultala wrote: > > > Our architecture(TCE) can have LOTS of registers. > > > > It seems r152019 changed some register bookkeeping data structures to > > 8-bit. This broke support for architectures with >255 registers. > > > > Please revert this change or make those register-related values at least > > 16 bits wide. > > I agree. We can limit the number of physregs to 64k, but no more. > > /jakob > >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120306/3ab33aae/attachment.html>
Jakob Stoklund Olesen
2012-Mar-15 18:14 UTC
[LLVMdev] commit r152019 broke architectures with more than 255 registers
On Mar 5, 2012, at 10:40 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:> > On Mar 5, 2012, at 5:39 AM, Heikki Kultala wrote: > >> Our architecture(TCE) can have LOTS of registers. >> >> It seems r152019 changed some register bookkeeping data structures to >> 8-bit. This broke support for architectures with >255 registers. >> >> Please revert this change or make those register-related values at least >> 16 bits wide. > > I agree. We can limit the number of physregs to 64k, but no more.I have reverted the commits that limited the concatenated register and instruction names to 64k. They would have caused problems for a 16k register target. Heikki, please let me know if you are having problems with the limits enforced by TableGen now. /jakob
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