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Hi, I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit of a background for the TCE project in general. I hope some of you will find it interesting :) http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html -- Pekka

2010/6/29 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi>: > Hi, > > I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit > of a background for the TCE project in general. I hope some of you will find > it interesting :) > > http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html I'll ask here (rather than the TCE list) because it's more about your use of LLVM rath...

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable VHDL and parallel program binaries. Processor customization points inc...

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported)...

Hi, I've been hitting my head to wall two days now. This is practically my first contact with InstrInfo.td files. Is there any tutorial how to make this kind of stuff? Or should I just keep on studying Sparc and other backends? So I added new intrinsic to llvm/include/llvm/TCEInstrinsics.td: def int_tce_customop : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_vararg_ty], [], "llvm.tce.customop">; I made opt pass that converts __custom_op() functions to calls to llvm.tce.customop calls. shell> grep llvm.tce.customop hello2.ll tail call vo...

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported)...

Announcing the Release of TTA-Based Codesign Environment (TCE) v1.2 TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customi...

TTA-Based Codesign Environment (TCE) v1.3 released -------------------------------------------------- TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable codesign flow from C programs do...

TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level langu...

TTA-Based Co-design Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the reg...

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset...

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset...

...o statically schedule the Instructions. Is this > possible by starting to modify the SelectionDAG Files ? > Or can i even build a "standalone" custom scheduler? > Thank you very much for any tipps. You might be interested to look at our recent scheduler generalization project in TCE [1]. In our case we convert from LLVM MachineInstructions to the IR of our custom scheduler (CFG+DDG) which is then converted back to fresh MachineBasicBlocks/MachineInstructions for assembly generation in the LLVM side. The first (non-TTA) target we are experimenting with is the Cell SPU. Eventu...

Hi there, i created a Function Pass to retrieve the Control/Data Flow Graph from a simple program, now i would like to statically schedule the Instructions. Is this possible by starting to modify the SelectionDAG Files ? Or can i even build a "standalone" custom scheduler? Thank you very much for any tipps. Ben

...ch I've been emailed by the oficianado is very unfamiliar and worrying. Where is the official syntax ? -- Without knowing if/how the sample gets mangled in email, he sent:-- LABEL Corepure64 MENU LABEL Corepure64 TEXT HELP Boot Corepure64 onbootpure64.lst ENDTEXT KERNEL /tce/boot/vmlinuz64 APPEND initrd=/boot/rootfs64.gz,/boot/modules64.gz loglevel=3 waitusb=5:LABEL ="USB16G" noswap tce=LABEL="USB16G"/corepure64/tce opt=LABEL="USB16G" home=LABEL="USB16G" --- Are these parameters part of syslinux syntax, or just extras whic...

...nd I have a feeling we are not the only ones. Especially now that the shared lib generation has been fixed, I predict use cases like ours won't be all that uncommon (clients to libLLVM*.so that use also libs like Boost that require RTTI). Mainly this is about a nuisance to need to ask users of TCE to recompile LLVM (which might be even installed from a precompiled binary for their distro) to be able to compile TCE. It's not easy to get rid of RTTI requiring code for us as we use Boost heavily in our derived MachineFunctionPasses. -- Pekka

Hi all, I think this master's thesis from our group could be of interest. It describes the "bridge" between the LLVM codegen and our custom TTA codegen in TCE: a runtime retargetable architecture description file driven LLVM compiler backend. The thesis might be useful also for people implementing backends for LLVM in general. http://tce.cs.tut.fi/doc/Compiler.pdf If you have any questions or comments, please direct them to me (I'm not the author o...

...ote: > Eli, > Yes I was referring to AllCallsAreTailCalls. I will take a look at how > to improve this. > > Nick, > Thanks. I agree that's the proper constrain to mark a call as > tailcall, however not being able to mark a call as tailcall shouldn't > completely kill TCE. (i.e. AllCallsAreTailCalls seems overly > limiting). I get it now. TailRecursionElimination.cpp does two optimizations, marking of tail and converting recursion to loops. I thought you were proposing a change to the marking of tail. Thanks for the example! "PR962" refers to "...

An include goes away in future patches which breaks compilation without this. Signed-off-by: Nicholas Piggin <npiggin at gmail.com> --- arch/powerpc/platforms/powernv/pci-ioda-tce.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c b/arch/powerpc/platforms/powernv/pci-ioda-tce.c index f923359d8afc..8eba6ece7808 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda-tce.c +++ b/arch/powerpc/platforms/powernv/pci-ioda-tce.c @@ -15,...

...M build system makes it really easy to turn RTTI on if you want it, so I don't see why this is any different than -fexceptions, -fvisibility-inlines-hidden, or one of many other code gen changing flags that you could build LLVM with. > Mainly this is about a nuisance to need to ask users of TCE to recompile > LLVM (which might be even installed from a precompiled binary for their distro) to be able to compile TCE. I'm dubious that doing that would actually work anyway. Since LLVM doesn't provide a stable API, being able to reuse a previously installed version of llvm is not v...