llvm dev - Feb 2011 - [LLVMdev] Adding "S" suffixed ARM and Thumb2 instructions

Hello everyone,

I've added the "S" suffixed versions of ARM and Thumb2
instructions to the
rest of those declared in tablegen. For example, "movs" or
"muls".
Besides, I propose the codegen optimization based on them, which removes
the redundant comparison in patterns like

orr r1, r2, r3         ---->        orrs r1, r2, r3
cmp r1, 0

This optimization has already shown nice acceleration, e.g. 3.3% in SQLite
on CortexA8.
I have some questions.

1)"neverHasSideEffects" in tablegen means that CPSR is not implicitly
defined, doesn't it?
2)What else can be done using that super "S" power?
3)Current optimization implementation works similar to peephole (peephole
pitiful cmp optimization was disabled),
right before ifcvt. Should I raise it up somewhere? What do you think is
the right place for such thing?
4)Consider the following C code:

int a, b, c;
...
a = b * c;
if (a > 0) { ... }

One gets the corresponding ARM assembler

mul r(a), r(b), r(c)
cmp r(a), 1
blt LABEL

// r(x) is the register where x is

The other cases ("if (a == 0)", "if (a < 0)") produce
expected

cmp r(a), 0

So what is the hidden idea of this resultant comparison with 1?
Where should I look for the code behind that logic?

Thanks,
  Vadim Markovtsev,
  ISP RAS.