Displaying 2 results from an estimated 2 matches for "cortexa8".
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2011 Feb 18
0
[LLVMdev] Adding "S" suffixed ARM and Thumb2 instructions
..., "movs" or "muls".
Besides, I propose the codegen optimization based on them, which removes
the redundant comparison in patterns like
orr r1, r2, r3 ----> orrs r1, r2, r3
cmp r1, 0
This optimization has already shown nice acceleration, e.g. 3.3% in SQLite
on CortexA8.
I have some questions.
1)"neverHasSideEffects" in tablegen means that CPSR is not implicitly
defined, doesn't it?
2)What else can be done using that super "S" power?
3)Current optimization implementation works similar to peephole (peephole
pitiful cmp optimization was disa...
2011 Feb 18
2
[LLVMdev] Adding "S" suffixed ARM/Thumb2 instructions
...such as add/adds,
and I leaved them untouched.
Besides, I propose the codegen optimization based on them, which removes the
redundant comparison in patterns like
orr r1, r2, r3 ----> orrs r1, r2, r3
cmp r1, 0
This optimization has shown nice acceleration, e.g. 3.3% in SQLite on
CortexA8 and works fine.
I have some questions though.
1)"neverHasSideEffects" in tablegen means that CPSR is not implicitly
defined, doesn't it?
2)What else can be done using that super "S" power?
3)Current optimization implementation works similar to peephole (peephole
pitiful cmp...