search for: orr

Hi, I am using robust regression, i.e. model.robust<-ltsreg(MXD~ORR,data=DATA). My question:- is there any way to determine the Robust Multiple R-Squared (as returned in the summary output in splus)? I found an equivalent model in the rrcov package which included R-square, residuals etc in it's list of components, but when I used this package the only results r...

...g: -(void)getCharacters:(unichar *)unicode {     NSRange range;     range.location = 0;     range.length = [self length];     printf("%p, %p\n", &range.location, &range.length); And before printf call I see an argument preparation, and one of the most interesting instruction     orr    r3, r2, #4 ;for address of range.length Does this mean llvm always expects "range" address aligned by 8 bytes? Is it possible to tweak it somehow by cmd line option for clang, e.g. to set 4-bytes alignment, and generate another code instead of orr, e.g. add? Best Regards, Alexey

...ing packed_endian_specific_integral is fairly efficient. For example, on x86_64 reading 32 bits with 1 2 and 4 byte alignment produces in all cases: movl (%rdi), %eax But on armv6 the aligned case is ldr r0, [r0] the 2 byte aligned case is ldrh r1, [r0, #2] ldrh r0, [r0] orr r0, r0, r1, lsl #16 and the unaligned case is ldrb r1, [r0] ldrb r2, [r0, #1] ldrb r3, [r0, #2] ldrb r0, [r0, #3] orr r1, r1, r2, lsl #8 orr r0, r3, r0, lsl #8 orr r0, r1, r0, lsl #16 On armv7 it is a single ldr on all cases. Now, I don't really kno...

...ys ARMv6 call convention is similar to ARMv7, and document refers to AAPCS, but also describes some discrepencies, like        The stack is 4-byte aligned at the point of function calls.              I faced here with bugs, due stack alignment, but as I wrote before, I think realignment or removing orr and use add instead could solve it.        Large data types (larger than 4 bytes) are 4-byte aligned.              I didn't yet test this case, but I think here could be the same pitfalls like with orr r0, r0, 4         Register R7 is used as a frame pointer              If I truly understood i...

...0.7421875 8 0.8515625 0.7265625 9 0.8203125 0.6953125 My question is: How do I sort by the first index (the values are 1:25) without losing the associated values per index value for the two columns(Gp17 and Gp4). I want ascending order (1:25) of the index values. Thank you in advance. -Mark Orr Postdoctoral Fellow Psychology Dept. Carnegie Mellon Univ. Pittsburgh, PA 15213

...and took in mind: compiler knows function signature, but runtime/loader doesn't. Now I don't have any other ideas instead of keeping signatures of problem functions in loader. > >> I faced here with bugs, due stack alignment, but as I wrote before, I think realignment or removing orr and use add instead could solve it. > >> Large data types (larger than 4 bytes) are 4-byte aligned. > > This is a big one. It means structs will be laid out differently > unless you're careful, but the most difficult aspect is that it > applies to function calls too. Consid...

...subnet. We are having problems we password protection associated with the shares. The first access to the samba server requests a userid -- this likely allows samba to understand which home share should be displayed. At this point, the client can access both the 'homes' share and the 'orr' share without ever entering a password -- this is a security issue for us. We need to figure out how to configure samba to enforce userid & password protection prior to allowing access to a share. Below is a copy of the smb.conf file that we are using for testing. [global] # workgro...

...bnet. We are having problems with password protection associated with the shares. The first access to the samba server requests a userid -- this likely allows samba to understand which home share should be displayed. At this point, the client can access both the 'homes' share and the 'orr' share without ever entering a password -- this is a security issue for us. We need to figure out how to configure samba to enforce userid & password protection prior to allowing access to a share. Below is a copy of the smb.conf file that we are using for testing. [global] # workgro...

...To: alexey.perevalov at hotmail.com > CC: llvmdev at cs.uiuc.edu > > On 20 April 2015 at 11:09, Alexey Perevalov > <alexey.perevalov at hotmail.com> wrote: >> And before printf call I see an argument preparation, and one of the most interesting instruction >> >> orr r3, r2, #4 ;for address of range.length > > This is certainly odd, and I can't reproduce the behaviour here. Even > if the stack itself is 8-byte aligned (it's not on iOS), that struct > would usually only be 4-byte aligned. LLVM shouldn't be using "orr" > there...

...he "attribute" levels are not accessible. Any suggestions on how to get get() to access these levels? From reading the get()'s help page, I don't think it will access the attributes. (my apologies for loosely using the term attributes, but I hope it is clear). Thanks, Mark Orr -- *********************************************** Mark G. Orr, PhD Heilbrunn Dept. of Population and Family Health Columbia University 60 Haven Ave., B-2 New York, NY 10032 Tele: 212-304-7823 Fax: 212-305-7024 www.columbia.edu/~mo2259

...s did not help me, although I'm sure I've either missed something or did not properly understand the internals of R. Any help or alternatives are much welcome; however, note, that alternatives should be general, because I desire this functionality for other tasks. Thanks in advance, Mark Orr [[alternative HTML version deleted]]

....order_8: ldmia r4, { r5-r12 } @ r5-r12 = mem[0..7] 0: ldrsh r14, [r0], #2 add r5, r5, #4096 @ Rounding constant str r0, [sp,#-4]! @ push r0 add r14, r14, r5, asr #13 @ (mem[0] + 4096) >> 13 + x[i] mov r5, #0x7f00 orr r5, r5, #0xff @ r5 = 32767 cmp r14, r5 movgt r14, r5 @ Clip positive cmn r14, r5 rsblt r14, r5, #0 @ Clip negative strh r14, [r2], #2 @ Write result to y[i] ldrsh r4, [r1] ldrsh r0, [r1, #2] rsb...

Martin Richtarsky <s at martinien.de> writes: > Output looks as follows [1] Seems sh_offset is missing? That is what readelf prints as Off > [17] .rela.text RELA 0000000000000000 071423 001728 18 > 1 4 8 The offset of rela text should have been aligned, but it is not. Can you report a bug on icc? As a work around using the gnu assembler if possible

...ns to tablegen. Those are, for example, "movs" or "muls". Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr r1, r2, r3 ----> orrs r1, r2, r3 cmp r1, 0 This optimization has shown nice acceleration, e.g. 3.3% in SQLite on CortexA8 and works fine. I have some questions though. 1)"neverHasSideEffects" in tablegen means that CPSR is not implicitly defined, doesn't it? 2)What...

Every man and his dog recommends you freeze rails, awesome! I''ve done that and setup my svn repo and been modify the code and checking in my updates. Now since 2.0.2 is here and I''m on 2.0.0 How do I get to 2.0.2 ?? Please include the impact that this has on the svn repository. Thanks :D --~--~---------~--~----~------------~-------~--~----~ You received this message because

...oston, MA 02111-1307 USA + */ +#include <asm/processor.h> +#include <asm/page.h> +#include <asm/system.h> +#include <asm/asm-macros.h> +#include <asm/cpu-domain.h> +#include <asm/asm-offsets.h> +#include <public/arch-arm.h> + +.macro SAVE_CONTEXT offset correction + sub lr, lr, #\correction + str r0, [sp, #-16] + str lr, [sp, #-12] + + mrs r0, spsr + mov lr, #\offset + str r0, [sp, #-8] + str lr, [sp, #-4] + + sub r0, sp, #16 + + msr cpsr_cxsf, #(PSR_I_BIT | PSR_F_BIT | PSR_MODE_SVC) + + sub sp, sp, #CTXT_FRAME_SIZE...

Hello everyone, I've added suffixed versions of ARM and Thumb2 instructions to tablegen. That is, for example, "movs" or "orrs". I implemented a rather simple codegen optimization which removes the comparison in patterns like orr r1, r2 ---> orrs r1, r2 cmp r1, 0 It works and have already shown nice acceleration (e.g., 3.3% in SQLite). I have a few questions. 1)"neverHasSideEffects" in t...

...ctor is tagged so that i is not selected again. However, after the loop, make.vector contains, for example, 1758 stds and 242 devs. Each iteration results in a different proportion of stds and devs (although close to the desired, not right on). Any help would be greatly apprecitated. -Mark Orr ________________________________ Mark G. Orr Postdoctoral Research Fellow Dept. of Neuroscience RM 825 Kennedy Center Albert Einstein College of Medicine Bronx, NY 10461 718-430-2610

...4 domain to which I do not have admin access, so so far as I can see pam_smb is the only option. Alternatively, does anyone know if it is possible to create an NT account whose only ability is to create machine accounts, which I could probably convince the NT domain admin to do for me? -- Martin Orr Linux Administrator, Methodist College Belfast

...stributions these days use > arm-linux-gnueabihf (or possibly arm-linux-gnueabi, the difference > being where floating-point arguments get passed). > You totally right. > If that's changed in your upgrade to 3.6, it might account for you > seeing "add" instead of "orr" now, too. > >>> I wouldn't rely on this. Trunk emits orr again, it's likely just a >>> random code perturbation and will bite you elsewhere without a real >>> solution. >>> >> Trunk of llvm's source code ) ? > > Yes. > > Tim...