Hello, I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of register rs to register rd and places the result in rd; add.cc rd, rs does the same and updates the condition codes. Can anybody point out an example of how such instructions should be defined in a corresponding xxInstrInfo.td file please? Sincerely, -- Lev. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100525/54f3a4e1/attachment.html>
On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote:> Hello, > > I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of register rs to register rd and places the result in rd; add.cc rd, rs does the same and updates the condition codes. Can anybody point out an example of how such instructions should be defined in a corresponding xxInstrInfo.td file please?ARM has similar instruction pairs, look at ADD/ADDS, SUB/SUBS in ARMInstrInfo.td /jakob
Thank you very very much for your answer! Am I correct in my understanding that "let Defs = [CPSR]" in the definition of AI1_bin_s_irs multiclass explains the effect of setting conditional codes to the TableGen in ARM's case? Sincerely, -- Lev. On Tue, May 25, 2010 at 6:49 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:> > On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote: > > > Hello, > > > > I'm just starting to work on a backend for a custom cpu. For some > instructions this cpu has two flavors: first performs an operation, and the > second performs an operation and updates condition codes (carry, zero, > overflow, negative etc) based on the outcome. For example: add rd,rs > instruction adds the contents of register rs to register rd and places the > result in rd; add.cc rd, rs does the same and updates the condition codes. > Can anybody point out an example of how such instructions should be defined > in a corresponding xxInstrInfo.td file please? > > ARM has similar instruction pairs, look at ADD/ADDS, SUB/SUBS in > ARMInstrInfo.td > > /jakob > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100526/31bc0ece/attachment.html>