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21bc8ece
2010 May 25
0
[LLVMdev] backend question
On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote:
> Hello,
>
> I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of
2010 May 26
1
[LLVMdev] backend question
...ng xxInstrInfo.td file please?
>
> ARM has similar instruction pairs, look at ADD/ADDS, SUB/SUBS in
> ARMInstrInfo.td
>
> /jakob
>
>
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2010 May 25
2
[LLVMdev] backend question
Hello,
I'm just starting to work on a backend for a custom cpu. For some
instructions this cpu has two flavors: first performs an operation, and the
second performs an operation and updates condition codes (carry, zero,
overflow, negative etc) based on the outcome. For example: add rd,rs
instruction adds the contents of register rs to register rd and places the
result in rd; add.cc rd, rs