search for: ai1_bin_s_irs

Displaying 3 results from an estimated 3 matches for "ai1_bin_s_irs".

2010 May 26
1
[LLVMdev] backend question
Thank you very very much for your answer! Am I correct in my understanding that "let Defs = [CPSR]" in the definition of AI1_bin_s_irs multiclass explains the effect of setting conditional codes to the TableGen in ARM's case? Sincerely, -- Lev. On Tue, May 25, 2010 at 6:49 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote: > > > Hello, > > &...
2010 May 25
0
[LLVMdev] backend question
On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote: > Hello, > > I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of
2010 May 25
2
[LLVMdev] backend question
Hello, I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of register rs to register rd and places the result in rd; add.cc rd, rs