llvm dev - May 2010 - [LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions

On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote:
> Ping. Anyone have any idea on how to fix this?
Does your getAllocatableSet() return a BitVector that is at least getNumRegs()
bits long? Otherwise this doesn't work:

  BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
  NonAllocatableRegs.flip();

Jakob, 
 Here is my implementation of getAllocatableSet:
BitVector 
AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF,
		const TargetRegisterClass *RC = NULL) const
{
	BitVector Allocatable(getNumRegs());
	Allocatable.clear();
	return Allocatable;
}


Micah

-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Monday, May 03, 2010 9:52 AM
To: Villmow, Micah
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Default behavior of DeadMachineInstructionElim deletes
all instructions


On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote:
> Ping. Anyone have any idea on how to fix this?
Does your getAllocatableSet() return a BitVector that is at least getNumRegs()
bits long? Otherwise this doesn't work:

  BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
  NonAllocatableRegs.flip();

On May 3, 2010, at 10:21 AM, Villmow, Micah wrote:
> Jakob, 
> Here is my implementation of getAllocatableSet:
> BitVector 
> AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF,
> 		const TargetRegisterClass *RC = NULL) const
> {
> 	BitVector Allocatable(getNumRegs());
> 	Allocatable.clear();
> 	return Allocatable;
> }
Well, there's your problem.

BitVector::clear() resets the size to 0, and callers of getAllocatableSet expect
a bit per physical register.

Please add an assert(NonAllocatableRegs.size() >= TRI->getNumRegs()) to
DeadMachineInstructionElim.

/jakob