search for: bitvector

Displaying 20 results from an estimated 155 matches for "bitvector".

2009 Jan 23
2
[LLVMdev] Small problem in BitVector.h
Hi, Doing some profiling of llc, I noticed that some bitvector operations took longer than usual. Then I noticed that too many copies of BitVector obejcts are created, even when such operations like &=, ^=, |= are performed on those bit vectors. I looked at the BitVector ADT implementation in BitVector.h and figured out that all assignment operations (exc...
2009 Jan 23
0
[LLVMdev] Small problem in BitVector.h
On Jan 23, 1:51 pm, Roman Levenstein <romix.l... at googlemail.com> wrote: > Hi, > > Doing some profiling of llc, I noticed that some bitvector operations > took longer than usual. Then I noticed that too many copies of > BitVector obejcts are created, even when such operations like &=, ^=, > |= are performed on those bit vectors. > > I looked at the BitVector ADT implementation in BitVector.h and > figured out that a...
2018 Sep 20
2
Interest in fast BitVector?
Some time ago I developed a fast BitVector class to use in some research here. It uses expression templates to fuse operation loops and runs much faster than the existing BitVector for some important use-cases. It also has the ability to efficiently report if a BitVector's contents changed after some operation. For example: ETBitVect...
2010 May 03
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote: > Ping. Anyone have any idea on how to fix this? Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); NonAllocatableRegs.flip();
2010 May 03
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Jakob, Here is my implementation of getAllocatableSet: BitVector AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF, const TargetRegisterClass *RC = NULL) const { BitVector Allocatable(getNumRegs()); Allocatable.clear(); return Allocatable; } Micah -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent:...
2007 Sep 06
2
[LLVMdev] [PATCH]: Add SparseBitmap implementation
On 9/4/07, Devang Patel <dpatel at apple.com> wrote: > > On Sep 4, 2007, at 4:36 PM, Daniel Berlin wrote: > > [snip] > > Don't forget to update ProgrammersManual.html "Picking the Right > Data Structure for a Task" section. :) It doesn't talk about bitvector at all. I'm not sure whether i should add it to set like containers, or add a section about bitsets that talks about bitvector and sparsebitvector. In either case, I think this should be a followup patch, but if you guys really want it done as part of this one, I will. > > - > Devan...
2011 Jan 30
2
problem reading file containing bit vector
...uot;00100000010000010000000000000000" When I read this the bitVec field is not read properly. Instead, the value showing is "Inf" . How should i read this file? as.is/colclasses field in read function is not helping me. Is there any package that can do bitwise operation(and/or) on bitVectors. bitops seems to do that but I need output in bitvector format only. Thanks Fahim -- Fahim Mohammad Bioinforformatics Lab University of Louisville Louisville, KY, USA Ph: +1-502-409-1167 [[alternative HTML version deleted]]
2008 Apr 03
3
[LLVMdev] choice between SSAPRE and bitvector aporach
Hi LLVMers, I am a PHD student in CS dept in UIUC, I am doing a project for Vikram's course, it is about PRE. I would like to know why you didn't choose SSAPRE in LLVM, since it seems to be more suitable for LLVM (it can operate directly on SSA form and avoid the conversion between SSA and bit-vector). Can anyone tell me the reason? Xuehai
2006 Aug 15
2
Windows build with Visual Studio 2005 - some success
...art, int end, int pos_inc); +inline Token *tk_set(Token *tk, char *text, int tlen, int start, int end, int pos_inc); Token *tk_set_no_len(Token *tk, char *text, int start, int end, int pos_inc); int tk_eq(Token *tk1, Token *tk2); int tk_cmp(Token *tk1, Token *tk2); --- ../../ferret/ferret/ext/bitvector.h 2006-08-15 15:25:38.096914500 +1000 +++ ext/bitvector.h 2006-08-15 14:49:59.479916700 +1000 @@ -23,7 +23,7 @@ void bv_write(BitVector *bv, Store *store, char *name); BitVector *bv_read(Store *store, char *name); void bv_scan_reset(BitVector *bv); -int bv_scan_next(BitVector *bv); -int bv_scan_...
2007 Sep 05
0
[LLVMdev] [PATCH]: Add SparseBitmap implementation
On Sep 4, 2007, at 4:36 PM, Daniel Berlin wrote: > Also, someone on IRC asked about the weird function naming > conventions. I know most of llvm uses mixedCase, but i copied the > style of BitVector, which has a weird mix. I'm happy to change it :) Yes please. By default, it is a good idea to follow llvm coding conventions instead of copying violation of coding style from existing code. Otherwise it pollutes code and, in future, gives someone one additional reason to not follow pre...
2008 Apr 04
0
[LLVMdev] choice between SSAPRE and bitvector aporach
On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > Hi LLVMers, > I am a PHD student in CS dept in UIUC, I am doing a project for > Vikram's course, it is about PRE. I would like to know why you didn't > choose SSAPRE in LLVM, since it seems to be more suitable for LLVM (it > can operate directly on SSA form and avoid the conversion between SSA > and bit-vector). Can
2007 Sep 04
6
[LLVMdev] [PATCH]: Add SparseBitmap implementation
...This is helpful for per-iteration pools of bitmaps, which is useful to points-to analysis. I was too lazy to make an operator new that emulated this functionality. Also, someone on IRC asked about the weird function naming conventions. I know most of llvm uses mixedCase, but i copied the style of BitVector, which has a weird mix. I'm happy to change it :) In any case, updated patch attached. -------------- next part -------------- A non-text attachment was scrubbed... Name: sparsebitmap.diff Type: text/x-diff Size: 18889 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-de...
2006 Feb 28
2
Most Popular Searches
Hi, I have an index where each document contains an untokenized ''url'' field. I would like to query the index for the most popular urls. In SQL I would do this via a Group By clause. Is there anything in Ferret that will do something similar? I found this discussion that proposed a solution involving TermEnums:
2008 Apr 11
0
[LLVMdev] choice between SSAPRE and bitvector aporach
On Apr 4, 2008, at 8:28 PM, Daniel Berlin wrote: > On Fri, Apr 4, 2008 at 5:58 PM, Vikram S. Adve <vadve at cs.uiuc.edu> > wrote: >> >> >> Dan, >> >> Doesn't the paper also assume the invariant that phi operands are >> effectively dead after the Phi, which is true right after SSA is >> constructed, but potentially not after
2013 Mar 21
2
[LLVMdev] How to describe a pointer that points to All memory(include global memory, heap, stack)?
..._MEMORY, HEAP_MEMORY. ALL_MEMORY contains GLOBAL_MEMORY, STACK_MEMORY, HEAP_MEMORY. e.g1: extern int * q; void f(int * p) { int a; *p = 0; //STMT1 *q = a; //STMT2 } For above case, both p and q pointed to ALL_MEMORY: p->ALL_MEMORY, q->ALL_MEMORY. And each STMT has two BitVectors to describe MayDef, MayUse. (I think the BitVector must be sparse, otherwise the alias-analysis module need too much memory to allocate for all BitVectors.) For STMT1, the MayDef={ALL_MEMORY}, MayUse={} For STMT2, the MayDef={ALL_MEMORY}, MayUse={'a'} --------------------- e.g2: ext...
2008 Apr 04
0
[LLVMdev] choice between SSAPRE and bitvector aporach
On Apr 4, 2008, at 4:51 PM, Daniel Berlin wrote: > On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> > wrote: >> On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: >>> Hi LLVMers, >>> I am a PHD student in CS dept in UIUC, I am doing a project for >>> Vikram's course, it is about PRE. I would like to know why you >>>
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
...default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything in my machine function is fine, after this pass, all instructions that are not function calls are deleted. I've tracked this issue down to the line: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); (In my case all registers defined in RegisterInfo.td) This function loops through all registers classes and sets all registers in the bitset that are allocatable. It then inverts the registers that are set to get the NonAllocatable registers and...
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
...default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything in my machine function is fine, after this pass, all instructions that are not function calls are deleted. I've tracked this issue down to the line: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); (In my case all registers defined in RegisterInfo.td) This function loops through all registers classes and sets all registers in the bitset that are allocatable. It then inverts the registers that are set to get the NonAllocatable registers and a...
2008 Apr 04
3
[LLVMdev] choice between SSAPRE and bitvector aporach
On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> wrote: > On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > > Hi LLVMers, > > I am a PHD student in CS dept in UIUC, I am doing a project for > > Vikram's course, it is about PRE. I would like to know why you didn't > > choose SSAPRE in LLVM, since it seems to be more suitable for
2008 Apr 05
2
[LLVMdev] choice between SSAPRE and bitvector aporach
On Fri, Apr 4, 2008 at 5:58 PM, Vikram S. Adve <vadve at cs.uiuc.edu> wrote: > On Apr 4, 2008, at 4:51 PM, Daniel Berlin wrote: > > > On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> > > wrote: > >> On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > >>> Hi LLVMers, > >>> I am a PHD student in CS dept in UIUC,