Displaying 20 results from an estimated 32 matches for "getnumreg".
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2010 May 03
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote:
> Ping. Anyone have any idea on how to fix this?
Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work:
BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
NonAllocatableRegs.flip();
2010 May 03
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Jakob,
Here is my implementation of getAllocatableSet:
BitVector
AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF,
const TargetRegisterClass *RC = NULL) const
{
BitVector Allocatable(getNumRegs());
Allocatable.clear();
return Allocatable;
}
Micah
-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
Sent: Monday, May 03, 2010 9:52 AM
To: Villmow, Micah
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Default behavior of DeadMachineInstructionElim delet...
2010 Sep 03
4
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
How do I get the total number of machine registers? I have currently
a MachineFunction and some derivatives.
How are the machine registers ordered internally? Can I index them off of a
zero based array or do I have to create a map to have them be zero based?
Thanks,
Jeff Kunkel
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2009 Dec 09
5
[LLVMdev] [PATCH] increase the max number of physical registers
...(proceding bottom-up),
> /// or ~0u if the register is not live.
> unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
>
> And this:
>
> std::fill(KillIndices, array_endof(KillIndices), ~0u);
>
> It should probably be dynamically allocated with TRI->getNumRegs() members instead.
Yep. David Goodwin is going to fix it.
Evan
>
> /jakob
>
2010 Aug 31
3
[LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.
.... To me this
makes no sense because
when I already have a register, why would I need to get it? Could someone
please explain the
transformation that is happening here?
/// getRegister - Return the specified register in the class.
///
unsigned getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register number out of range!");
return RegsBegin[i];
}
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2010 Jul 06
1
[LLVMdev] [PATCH] increase the max number of physical registers
...gt; /// or ~0u if the register is not live.
>> unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
>>
>> And this:
>>
>> std::fill(KillIndices, array_endof(KillIndices), ~0u);
>>
>> It should probably be dynamically allocated with TRI->getNumRegs() members instead.
>
> Yep. David Goodwin is going to fix it.
>
> Evan
>
>> /jakob
>>
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.ui...
2009 Dec 08
2
[LLVMdev] [PATCH] increase the max number of physical registers
This caused a massive slow down to post-ra scheduler (llc -O3 on x86, -O2 on ARM). I'm going to revert it for now until it has been addressed.
Evan
On Dec 7, 2009, at 11:39 AM, Dan Gohman wrote:
>
> On Dec 7, 2009, at 11:15 AM, Pekka Jääskeläinen wrote:
>
>> Here's the actual patch, sorry ;)
>
> Applied in r90789.
>
> Dan
>
>
>
2009 Dec 08
0
[LLVMdev] [PATCH] increase the max number of physical registers
...s - The index of the most recent kill (proceding bottom-up),
/// or ~0u if the register is not live.
unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
And this:
std::fill(KillIndices, array_endof(KillIndices), ~0u);
It should probably be dynamically allocated with TRI->getNumRegs() members instead.
/jakob
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
TargetRegisterInfo::getNumRegs().
Generally, it's best not to make any assumptions about the internal ordering or numbering if you can avoid it. What are you looking to do?
-Jim
On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote:
> How do I get the total number of machine registers? I have currently a MachineFunction and...
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
...get the total number of machine registers? I have currently a MachineFunction and some derivatives.
>
> How are the machine registers ordered internally? Can I index them off of a zero based array or do I have to create a map to have them be zero based?
Registers are numbered from 1 to TRI::getNumRegs()-1. Reg 0 is not a register, but it is counted by getNumRegs.
They are currently sorted by name by StringRef::compare_numeric(), but try to avoid depending on that. It could easily change, I have been experimenting with the performance impact of a topological order.
/jakob
2010 Sep 01
0
[LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.
...; when I already have a register, why would I need to get it? Could someone
> please explain the
> transformation that is happening here?
>
> /// getRegister - Return the specified register in the class.
> ///
> unsigned getRegister(unsigned i) const {
> assert(i < getNumRegs() && "Register number out of range!");
> return RegsBegin[i];
> }
>
>
>
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2010 Sep 03
2
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
...ister and those are
taken care of ever so cleverly.
If this can be done without an extra lookup, it would improve performance. I
have one too many as is in some parts.
Thanks,
Jeff Kunkel
On Fri, Sep 3, 2010 at 12:57 PM, Jim Grosbach <grosbach at apple.com> wrote:
> TargetRegisterInfo::getNumRegs().
>
> Generally, it's best not to make any assumptions about the internal
> ordering or numbering if you can avoid it. What are you looking to do?
>
> -Jim
>
> On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote:
>
> > How do I get the total number of machine registers...
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
...Regards,
Jim
>
> If this can be done without an extra lookup, it would improve performance. I have one too many as is in some parts.
>
> Thanks,
> Jeff Kunkel
>
> On Fri, Sep 3, 2010 at 12:57 PM, Jim Grosbach <grosbach at apple.com> wrote:
> TargetRegisterInfo::getNumRegs().
>
> Generally, it's best not to make any assumptions about the internal ordering or numbering if you can avoid it. What are you looking to do?
>
> -Jim
>
> On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote:
>
> > How do I get the total number of machine registers?...
2010 Sep 02
0
[LLVMdev] [PATCH] increase the max number of physical registers
...ister is not live.
>>> unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
>>>
>>> And this:
>>>
>>> std::fill(KillIndices, array_endof(KillIndices), ~0u);
>>>
>>> It should probably be dynamically allocated with TRI->getNumRegs() members instead.
>>
>> Yep. David Goodwin is going to fix it.
>>
>> Evan
>>
>>> /jakob
>>>
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http...
2010 Sep 02
2
[LLVMdev] [PATCH] increase the max number of physical registers
...ister is not live.
>>> unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
>>>
>>> And this:
>>>
>>> std::fill(KillIndices, array_endof(KillIndices), ~0u);
>>>
>>> It should probably be dynamically allocated with TRI->getNumRegs() members instead.
>> Yep. David Goodwin is going to fix it.
>>
>> Evan
>>
>>> /jakob
>>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.ed...
2010 Apr 29
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Ping. Anyone have any idea on how to fix this?
Thanks,
Micah
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Wednesday, April 14, 2010 2:28 PM
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Dale,
Yeah that is correct, so that isn't the problem, not sure
2004 Sep 26
2
[LLVMdev] patches and scons
...lt;int> > classPairGaps(numSchedClasses,
std::vector<int>(numSchedClasses,0));
there're also other cases in
llvm\lib\Bytecode\Reader\Reader.cpp(1484) : error C2057: expected
constant expression
llvm/lib/CodeGen/LiveVariables.cpp', # MachineInstr
*PhysRegInfoA[RegInfo->getNumRegs()]; C99
but they are too complicated for this evening ;-)
* IsInf.cpp
VC has _finite in <float.h>. I think it's needed to integrate the
#if dance in IsInf.cpp with
#elif HAVE__FINITE_IN_FLOAT_H
# include <float.h>
static int isinf(double x) { return !_finite(x); }...
2004 Sep 03
4
[LLVMdev] diffs for vc7.1
...und, even with argument-dependent lookup
* C99 Arrays... forgive me if I don't provide a patch to standard
vectors...
llvm\lib\Bytecode\Reader\Reader.cpp(1483) : error C2057: expected
constant expression
llvm/lib/CodeGen/LiveVariables.cpp, # MachineInstr
*PhysRegInfoA[RegInfo->getNumRegs()]; C99 array
llvm/lib/Target/TargetSchedInfo.cpp, # int
classPairGaps[numSchedClasses][numSchedClasses]; C99 array
The next bigger problem is that the compiler complains about this kind
of construct...
<snip>
for (BasicBlock::iterator I = Dest->begin(); PHINode *PN =
dyn_cast&l...
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Dale,
Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers.
If there is a function call, there is a copy from virtual register space to the functions
2016 Jun 20
2
FireFox-46.0.1 build with interprocedural register allocation enabled
On Mon, Jun 20, 2016 at 10:05 PM, Sanjoy Das <sanjoy at playingwithpointers.com
> wrote:
> Hi Vivek,
>
> vivek pandya wrote:
>
> > For Octane and Kraken I have run them 4 times and above result is
> > geometric mean. For Octane standard deviation (SD) is
> > 918.54 (NO_IPRA) and 597.82 (With_IPRA). For Kraken unfortunately I
> > don't have readings