I'm looking at the instruction formats and I can't grok the comments.
For
example:
// SSSE3 Instruction Templates:
//
// SS38I - SSSE3 instructions with T8 prefix.
// SS3AI - SSSE3 instructions with TA prefix.
//
Where are these prefix names coming from? I can't find any mention of them
in
the Intel literature.
Also, there's this curious table:
// Prefix byte classes which are used to indicate to the ad-hoc machine code
// emitter that various prefix bytes are required.
class OpSize { bit hasOpSizePrefix = 1; }
class AdSize { bit hasAdSizePrefix = 1; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
class TB { bits<4> Prefix = 1; }
class REP { bits<4> Prefix = 2; }
class D8 { bits<4> Prefix = 3; }
class D9 { bits<4> Prefix = 4; }
class DA { bits<4> Prefix = 5; }
class DB { bits<4> Prefix = 6; }
class DC { bits<4> Prefix = 7; }
class DD { bits<4> Prefix = 8; }
class DE { bits<4> Prefix = 9; }
class DF { bits<4> Prefix = 10; }
class XD { bits<4> Prefix = 11; }
class XS { bits<4> Prefix = 12; }
class T8 { bits<4> Prefix = 13; }
class TA { bits<4> Prefix = 14; }
Are these Prefix values special at all or do they just serve as unique
identifiers within LLVM?
I'll try adding documentation to this stuff as soon as I figure out what it
is.
-Dave
On Mar 23, 2009, at 12:57 PM, David A. Greene wrote:> I'm looking at the instruction formats and I can't grok the > comments. For > example: > > // SSSE3 Instruction Templates: > // > // SS38I - SSSE3 instructions with T8 prefix. > // SS3AI - SSSE3 instructions with TA prefix. > // > > Where are these prefix names coming from? I can't find any mention > of them in > the Intel literature.They come from the fact that the SSSE3 instructions begin with 0F 38 or 0F 3A.> > Also, there's this curious table: > > // Prefix byte classes which are used to indicate to the ad-hoc > machine code > // emitter that various prefix bytes are required. > class OpSize { bit hasOpSizePrefix = 1; } > class AdSize { bit hasAdSizePrefix = 1; } > class REX_W { bit hasREX_WPrefix = 1; } > class LOCK { bit hasLockPrefix = 1; } > class TB { bits<4> Prefix = 1; } > class REP { bits<4> Prefix = 2; } > class D8 { bits<4> Prefix = 3; } > class D9 { bits<4> Prefix = 4; } > class DA { bits<4> Prefix = 5; } > class DB { bits<4> Prefix = 6; } > class DC { bits<4> Prefix = 7; } > class DD { bits<4> Prefix = 8; } > class DE { bits<4> Prefix = 9; } > class DF { bits<4> Prefix = 10; } > class XD { bits<4> Prefix = 11; } > class XS { bits<4> Prefix = 12; } > class T8 { bits<4> Prefix = 13; } > class TA { bits<4> Prefix = 14; } > > Are these Prefix values special at all or do they just serve as unique > identifiers within LLVM?They are just unique identifiers in LLVM.
On Monday 23 March 2009 16:38, Nate Begeman wrote:> > // SSSE3 Instruction Templates: > > // > > // SS38I - SSSE3 instructions with T8 prefix. > > // SS3AI - SSSE3 instructions with TA prefix. > > // > > > > Where are these prefix names coming from? I can't find any mention > > of them in > > the Intel literature. > > They come from the fact that the SSSE3 instructions begin with 0F 38 > or 0F 3A.I sort of guessed that, but why "T?" For (T)hree?> > Also, there's this curious table: > > > > // Prefix byte classes which are used to indicate to the ad-hoc > > machine code > > // emitter that various prefix bytes are required. > > class OpSize { bit hasOpSizePrefix = 1; } > > class AdSize { bit hasAdSizePrefix = 1; } > > class REX_W { bit hasREX_WPrefix = 1; } > > class LOCK { bit hasLockPrefix = 1; } > > class TB { bits<4> Prefix = 1; } > > class REP { bits<4> Prefix = 2; } > > class D8 { bits<4> Prefix = 3; } > > class D9 { bits<4> Prefix = 4; } > > class DA { bits<4> Prefix = 5; } > > class DB { bits<4> Prefix = 6; } > > class DC { bits<4> Prefix = 7; } > > class DD { bits<4> Prefix = 8; } > > class DE { bits<4> Prefix = 9; } > > class DF { bits<4> Prefix = 10; } > > class XD { bits<4> Prefix = 11; } > > class XS { bits<4> Prefix = 12; } > > class T8 { bits<4> Prefix = 13; } > > class TA { bits<4> Prefix = 14; } > > > > Are these Prefix values special at all or do they just serve as unique > > identifiers within LLVM? > > They are just unique identifiers in LLVM.Ok. X86CodeEmitter has this for XS / XD: case X86II::XS: // F3 0F case X86II::XD: // F2 0F Why "XS" and "XD?" (X)MM (S)ingle and (X)MM (D)ouble? -Dave