Displaying 7 results from an estimated 7 matches for "adsize".
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2009 Mar 23
2
[LLVMdev] X86InstrFormats.td Question
...names coming from? I can't find any mention of them in
the Intel literature.
Also, there's this curious table:
// Prefix byte classes which are used to indicate to the ad-hoc machine code
// emitter that various prefix bytes are required.
class OpSize { bit hasOpSizePrefix = 1; }
class AdSize { bit hasAdSizePrefix = 1; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
class TB { bits<4> Prefix = 1; }
class REP { bits<4> Prefix = 2; }
class D8 { bits<4> Prefix = 3; }
class D9 { bits<4> Prefix = 4; }
class DA { bi...
2018 Mar 28
0
x86 instruction format which takes a single 64-bit immediate
...rex.r, rex.x, rex.b, etc. See format list below.
ImmT - Determines the size of the immediate, if any at the end of the instruction.
OpSize - Used to inciate instructions that need a 0x66 operand size prefix to encode 16-bit operands in 32 mode or 32-bit operands in 16-bit mode.
AdSize - Used to mark instructions that need to emit a 0x67 address size prefix in 32-bit mode or 16-bit mode. This is rarely used and is only needed by instructions that don't use an address encoded in modrm/sib.
OpPrefix - Encodes whether the instruction requires a 0x66, 0xf2, or 0xf3...
2018 Mar 28
4
x86 instruction format which takes a single 64-bit immediate
I am attempting to create an instruction which takes a single 64-bit
immediate. This doesn't seem like a thing that would exist already (because
who needs an instruction which just takes an immediate?) How might I
implement this easily? Perhaps I could use a format which encodes a
register, which is then unused?
Thanks for the help.
Gus
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An HTML
2014 Jan 16
2
[LLVMdev] Some bugs in x86 disasm (llvm-mc)
I believe I have now fixed the 0x64 0xa1 0x00 0x00 0x00 0x00 bug in r199364.
On Wed, Jan 15, 2014 at 10:53 AM, Craig Topper <craig.topper at gmail.com>wrote:
> To fix it we need to change offset8/offset16/etc to have two suboperands
> and update the printer to understand that. Also update the disassembler to
> add the segment to the MCInst when its creating it. When I did these
2009 Mar 23
0
[LLVMdev] X86InstrFormats.td Question
...instructions begin with 0F 38
or 0F 3A.
>
> Also, there's this curious table:
>
> // Prefix byte classes which are used to indicate to the ad-hoc
> machine code
> // emitter that various prefix bytes are required.
> class OpSize { bit hasOpSizePrefix = 1; }
> class AdSize { bit hasAdSizePrefix = 1; }
> class REX_W { bit hasREX_WPrefix = 1; }
> class LOCK { bit hasLockPrefix = 1; }
> class TB { bits<4> Prefix = 1; }
> class REP { bits<4> Prefix = 2; }
> class D8 { bits<4> Prefix = 3; }
> class D9 { bits<4> P...
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
...sc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
> +
> + // Emit the operand size opcode prefix as needed.
> + if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
> +
> + // Emit the address size opcode prefix as needed.
> + if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
> +
> + bool Need0FPrefix = false;
> + switch (Desc->TSFlags & X86II::Op0Mask) {
> + case X86II::TB: // Two-byte opcode prefix
> + case X86II::T8: // 0F 38
> + case X86II::TA: // 0F 3A
> + Need0FPrefix = true;
> + break;
> + case X86II:...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And