search for: opsize

...ph =3D (void *)skb->nh.iph + skb->nh.iph->ihl*4; + optend =3D (unsigned char *)tcph + tcph->doff*4; ptr =3D (unsigned char *)(tcph+1); =20 dir =3D CTINFO2DIR(ctinfo); =20 - while (length > 0) { - int opcode =3D *ptr++; + while (ptr < optend) { + int opcode =3D ptr[0]; int opsize; =20 switch (opcode) { case TCPOPT_EOL: - return !sack_adjusted; + return; case TCPOPT_NOP: - length--; + ptr++; continue; default: - opsize =3D *ptr++; - if (opsize > length) /* no partial opts */ - return !sack_adjusted; + opsize =3D ptr[1]; + /* no partial...

...Version: All Status: NEW Severity: minor Priority: P2 Component: nf_conntrack AssignedTo: netfilter-buglog at lists.netfilter.org ReportedBy: mbuilov at gmail.com Estimated Hours: 0.0 Incorrect handling of invalid TCP option with too big opsize may lead to read access beyond tcp-packet or buffer allocated on stack. in net/netfilter/nf_conntrack_proto_tcp.c: 397 while (length > 0) { 398 int opcode=*ptr++; 399 int opsize; 400 401 switch (opcode) { 402 case TCPOPT_EOL: 403 return;...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG; defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX, VEX_LIG; let Pattern = []<dag> in { defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, "comiss", SSEPackedSingle>, TB, VEX, VEX_LIG; d...

...(outs info.regClass:$r1), (ins info.regClass:$r2, info.regClass:$r3), instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr, [(set info.regClass:$r1, (opNode info.regClass:$r2, info.regClass:$r3))], itin > { let isFloat = info.isFloat; let opsize = info.sizeCode; } Is there a way to do something like: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (...

...128-bit PXOR instructions in the generated code. I traced it down to the following definition in X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the trick. I noticed that TOT has a different definition and I tried substituting that as well but again no luck. Is there a simple way to make it work with LLVM 3.0 or should I consider updating to a later version? Thanks, N...

...with TA prefix. // Where are these prefix names coming from? I can't find any mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class TB { bits<4> Prefix = 1; } class REP { bits<4> Prefix = 2; } class D8 { bits<4> Prefix = 3; } class D9 { bit...

...and the ModRM byte. Form - Classifies how operands are encoded into the various fields that encode operands, i.e. modrm.reg, modrm.rm, vex.vvvv, rex.r, rex.x, rex.b, etc. See format list below. ImmT - Determines the size of the immediate, if any at the end of the instruction. OpSize - Used to inciate instructions that need a 0x66 operand size prefix to encode 16-bit operands in 32 mode or 32-bit operands in 16-bit mode. AdSize - Used to mark instructions that need to emit a 0x67 address size prefix in 32-bit mode or 16-bit mode. This is rarely used and is only...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

...te: ‘OpSrcValueOffset’ was declared here lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6033: warning: ‘OpSrcValue’ may be used uninitialized in this function lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6033: note: ‘OpSrcValue’ was declared here lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6032: warning: ‘OpSize’ may be used uninitialized in this function lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6032: note: ‘OpSize’ was declared here

...s without generating loads. e.g. pxor xmm0, xmm0 Here is an example of what i am referring to snipped from X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; My question is why was there a need to define such a pseudo instruction? Wouldn't it be cleaner to use a def: Pat<> which selects: pxor $dst, $dst from: [(set FR32:$dst, fp32imm0)] ? Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed.....

...the generated > code. > > I traced it down to the following definition in X86InstrSSE.td: > >   def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", >                    [(set FR32:$dst, fp32imm0)]>, >                    Requires<[HasSSE1]>, TB, OpSize; > > I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the > trick. I noticed that TOT has a different definition and I tried > substituting that as well but again no luck. Is there a simple way to > make it work with LLVM 3.0 or should I consider updating to a late...

...rature. They come from the fact that the SSSE3 instructions begin with 0F 38 or 0F 3A. > > Also, there's this curious table: > > // Prefix byte classes which are used to indicate to the ad-hoc > machine code > // emitter that various prefix bytes are required. > class OpSize { bit hasOpSizePrefix = 1; } > class AdSize { bit hasAdSizePrefix = 1; } > class REX_W { bit hasREX_WPrefix = 1; } > class LOCK { bit hasLockPrefix = 1; } > class TB { bits<4> Prefix = 1; } > class REP { bits<4> Prefix = 2; } > class D8 { bits<4> Pr...

I believe I have now fixed the 0x64 0xa1 0x00 0x00 0x00 0x00 bug in r199364. On Wed, Jan 15, 2014 at 10:53 AM, Craig Topper <craig.topper at gmail.com>wrote: > To fix it we need to change offset8/offset16/etc to have two suboperands > and update the printer to understand that. Also update the disassembler to > add the segment to the MCInst when its creating it. When I did these

...+ return getRoot(); + + std::vector<SDOperand> DependentMemOps, IndependentMemOps; + + for (std::vector<SDOperand>::iterator I = PendingLoads.begin(), + E = PendingLoads.end(); I != E; ++I) { + SDOperand PendingMemOp = *I; + + SDOperand OpPtr; + int64_t OpSize; + const Value *OpValue; + int OpOffset; + FindAliasInfo(PendingMemOp.Val, OpPtr, OpSize, OpValue, OpOffset); + + if (isAlias(OpPtr, OpSize, OpValue, OpOffset, + StoreAddr, StoreSize, StoreAddrValue, StoreOffset)) { + DependentMemOps.push_back(PendingMemO...

..."shl{b}\t{%cl, $dst|$dst, %CL}", [(set GR8:$dst, (shl GR8:$src, %CL))]>; def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), "shl{w}\t{%cl, $dst|$dst, %CL}", [(set GR16:$dst, (shl GR16:$src, %CL))]>, OpSize; def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), "shl{l}\t{%cl, $dst|$dst, %CL}", [(set GR32:$dst, (shl GR32:$src, %CL))]>; } // Uses = [CL] Needs to be: let Uses = [CL] in { def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :...

..."mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, (load addr:$src))]>, OpSize; def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, (load addr:$src))]>; For my target processor, only the types of operands (e.g. rm) are really important. The size is encoded into the o...

...rc2, $src1|$src1, $src2}", > [(set GR32:$dst, > - (int_x86_sse42_crc32_16 GR32:$src1, > + (int_x86_sse42_crc32_32_16 GR32:$src1, > (load addr:$src2)))]>, > OpSize; > - def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), > + def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), > (ins GR32:$src1, GR16:$src2), > "crc32{w} \t{$src2, $src1|$src1, $src2}", >...

...outs), (ins i8mem:$src), // AX/[mem8] = AL,AH "div{b}\t$src", [], IIC_DIV8_MEM>; let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX "div{w}\t$src", [], IIC_DIV16>, OpSize; let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), "div{l}\t$src", [], IIC_DIV32>; // RDX:RAX/[mem64] = RAX,RDX let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in def DIV64m : RI<0x...

..."mov{b} {$src, $dst|$dst, $src}", > [(set GR8:$dst, (load addr:$src))]>; > def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), > "mov{w} {$src, $dst|$dst, $src}", > [(set GR16:$dst, (load addr:$src))]>, OpSize; > def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), > "mov{l} {$src, $dst|$dst, $src}", > [(set GR32:$dst, (load addr:$src))]>; We must do this, because they perform different operations. Specifically, the loads all read a diff...