search for: rex_w

Utilize some of the additions in the prior patches to clean up other code: - keep track of REP prefixes in only one variable - use REX_W in a few more places (instead of a literal number) Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -304,6 +304,10 @@ union vex { ptr[1] = rex | REX_PREFIX; \ } while (0) +#define rep_pref...

...mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class TB { bits<4> Prefix = 1; } class REP { bits<4> Prefix = 2; } class D8 { bits<4> Prefix = 3; } class D9 { bits<4> Prefix = 4; } class DA { bits<4> Prefix = 5; } class DB {...

...; > Also, there's this curious table: > > // Prefix byte classes which are used to indicate to the ad-hoc > machine code > // emitter that various prefix bytes are required. > class OpSize { bit hasOpSizePrefix = 1; } > class AdSize { bit hasAdSizePrefix = 1; } > class REX_W { bit hasREX_WPrefix = 1; } > class LOCK { bit hasLockPrefix = 1; } > class TB { bits<4> Prefix = 1; } > class REP { bits<4> Prefix = 2; } > class D8 { bits<4> Prefix = 3; } > class D9 { bits<4> Prefix = 4; } > class DA { bits<4>...

...$src2, $src1|$src1, $src2}", > [(set GR64:$dst, > - (int_x86_sse42_crc64_8 GR64:$src1, > + (int_x86_sse42_crc32_64_8 GR64:$src1, > (load addr:$src2)))]>, > REX_W; > - def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst), > + def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst), > (ins GR64:$src1, GR8:$src2), > "crc32{b} \t{$src2, $src1|$src1, $src2}", >...

...this is primarily used by SSE instructions where 0x66 is different than the 0x66 operand size prefix above. OpMap - Which one of the opcode maps this instruction belows to. Corresponds to the one byte, two byte, three byte 0x0f 0x38, three byte 0x0f 0x3a, etc. maps from the Intel SDM. hasREX_WPrefix - Indicates the instruction requires the REX.W it to be set. hasLockPrefix - Indicates the instruction should be encoded with a 0xF0 lock prefix. hasREPPrefix - Indicates the instruction should be encoded with a 0xF3 rep prefix. OpcEnc - Which encoding scheme this instruction us...

...t MachineInstr &MI) { > - unsigned REX = 0; > - const TargetInstrDesc &Desc = MI.getDesc(); > - > - // Pseudo instructions do not need REX prefix byte. > - if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) > - return 0; > - if (Desc.TSFlags & X86II::REX_W) > - REX |= 1 << 3; > - > - unsigned NumOps = Desc.getNumOperands(); > - if (NumOps) { > - bool isTwoAddr = NumOps > 1 && > - Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; > - > - // If it accesses SPL, BPL, SIL, or DIL, then it requires...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And