llvm dev - Jan 2009 - [LLVMdev] Possible bug in LiveIntervals (triggered on the XCore target)?

On Jan 13, 2009, at 11:20 AM, Richard Osborne <richard at xmos.com> wrote:
> Roman Levenstein wrote:
>> Hi again,
>>
>> Now, after I fixed the graph coloring regalloc bug that was triggered
>> by the ARM target, I continue testing and found another bug, this  
>> time
>> on the XCore target. First I thought that it is again specific to my
>> register allocator, but it seems to be trigerred also by LLVM's
>> linearscan register allocator.
>>
>> I don't know if the XCore target is stable enough in LLVM, or may  
>> be I
>> should just safely skip it during testing because it is not mature
>> yet. Anyway, I report it here - may be it is of some interest.
>>
>> The crash happens in LiveIntervalsAnalysis, inside the spilling
>> function. From what I observe, I'd say it is related to
>> rematerializable intervals.
>>
>> The assertion says:
>> /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142:
>> llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int):
>> Assertion `I != r2iMap_.end() && "Interval does not exist
for
>> register"' failed.
>>
>> I attach the BC file generated by bugpoint, so that you can  
>> reproduce it.
>>
>> The command-line I use is:
>> llc --regalloc=linearscan --march=xcore  -f bugpoint-reduced- 
>> simplified.bc
>>
>> Any ideas about the reasons of this bug?
>>
>> Thanks,
>>  -Roman
> It looks like it is trying to rematerialize a load from fixed stack  
> slot (LDWSP instruction). This has an implicit use of the SP  
> register which is non allocatable.
>
> rewriteInstructionsForSpills calls getReMatImplicitUse which returns  
> the SP register. This is then followed by a call to getInterval for  
> this register which fails. The attached patch causes  
> getReMatImplicitUse to ignore non allocatable physical registers,  
> which fixes the issue for me. Does this look OK?
This patch assumes non allocatable registers are available at any  
point. I don't think that's a safe. Can you change LDWSP so it
doesn't
implicitly use sp? Once the frame index object is lowered by PEI, it  
can be rewritten to explicitly use sp. Would that work?

Evan
>
>
> -- 
> Richard Osborne | XMOS
> http://www.xmos.com
>
>
> Index: lib/CodeGen/LiveIntervalAnalysis.cpp  
> ===================================================================  
> --- lib/CodeGen/LiveIntervalAnalysis.cpp	(revision 60478) +++ lib/ 
> CodeGen/LiveIntervalAnalysis.cpp	(working copy) @@ -820,6 +820,9 @@  
> unsigned Reg = MO.getReg(); if (Reg == 0 || Reg == li.reg) continue;  
> + if (TargetRegisterInfo::isPhysicalRegister(Reg) && + ! 
> allocatableRegs_[Reg]) + continue; // FIXME: For now, only remat MI  
> with at most one register operand. assert(!RegOp && "Can't
> rematerialize instruction with multiple register operand!");
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Evan Cheng wrote:
> On Jan 13, 2009, at 11:20 AM, Richard Osborne <richard at xmos.com>
wrote:
>
>   
>> Roman Levenstein wrote:
>>     
>>> Hi again,
>>>
>>> Now, after I fixed the graph coloring regalloc bug that was
triggered
>>> by the ARM target, I continue testing and found another bug, this  
>>> time
>>> on the XCore target. First I thought that it is again specific to
my
>>> register allocator, but it seems to be trigerred also by LLVM's
>>> linearscan register allocator.
>>>
>>> I don't know if the XCore target is stable enough in LLVM, or
may
>>> be I
>>> should just safely skip it during testing because it is not mature
>>> yet. Anyway, I report it here - may be it is of some interest.
>>>
>>> The crash happens in LiveIntervalsAnalysis, inside the spilling
>>> function. From what I observe, I'd say it is related to
>>> rematerializable intervals.
>>>
>>> The assertion says:
>>> /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142:
>>> llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned
int):
>>> Assertion `I != r2iMap_.end() && "Interval does not
exist for
>>> register"' failed.
>>>
>>> I attach the BC file generated by bugpoint, so that you can  
>>> reproduce it.
>>>
>>> The command-line I use is:
>>> llc --regalloc=linearscan --march=xcore  -f bugpoint-reduced- 
>>> simplified.bc
>>>
>>> Any ideas about the reasons of this bug?
>>>
>>> Thanks,
>>>  -Roman
>>>       
>> It looks like it is trying to rematerialize a load from fixed stack  
>> slot (LDWSP instruction). This has an implicit use of the SP  
>> register which is non allocatable.
>>
>> rewriteInstructionsForSpills calls getReMatImplicitUse which returns  
>> the SP register. This is then followed by a call to getInterval for  
>> this register which fails. The attached patch causes  
>> getReMatImplicitUse to ignore non allocatable physical registers,  
>> which fixes the issue for me. Does this look OK?
>>     
>
> This patch assumes non allocatable registers are available at any  
> point. I don't think that's a safe. Can you change LDWSP so it
doesn't
> implicitly use sp? Once the frame index object is lowered by PEI, it  
> can be rewritten to explicitly use sp. Would that work?
>
> Evan
OK, that make sense, I'll take a look at changing this. I've added a bug
for the issue:

http://llvm.org/bugs/show_bug.cgi?id=3324

There is currently no Backend: XCore component in bugzilla so I've put 
it under new-bugs. Could someone add this component for me.

Thanks

-- 
Richard Osborne | XMOS
http://www.xmos.com

On Jan 14, 2009, at 3:14 AM, Richard Osborne wrote:
>> Evan
> OK, that make sense, I'll take a look at changing this. I've added
a
> bug
> for the issue:
>
> http://llvm.org/bugs/show_bug.cgi?id=3324
>
> There is currently no Backend: XCore component in bugzilla so I've put
> it under new-bugs. Could someone add this component for me.
Added.  You should also be automatically CC'd on anything filed to  
that component,

-Chris