llvm dev - Jan 2009 - [LLVMdev] Look-ahead instruction selection

In .td file, if the pattern to match the DAG is:

(vector_shuffle (mul build_vector, build_vector))

is it possible to return 'mul' (SDNode*) instead of returning the first
'vector_shuffle'?

It seems to me that the default instruction selector can only return the
'root' node of the pattern.

Alex.
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On Mon, Jan 5, 2009 at 2:32 PM, Alex <alex.lavoro.propio at gmail.com>
wrote:
> In .td file, if the pattern to match the DAG is:
>
> (vector_shuffle (mul build_vector, build_vector))
>
> is it possible to return 'mul' (SDNode*) instead of returning the
first
> 'vector_shuffle'?
>
> It seems to me that the default instruction selector can only return the
> 'root' node of the pattern.
The simplest thing to do is to map a vector_shuffle to another
vector_shuffle; there shouldn't be any issues with that, I think.  Is
there some reason you don't want to write it that way?

Note that you can use a custom PatFrag to match an instruction with a
single use... see, for example, "and_su" in X86InstrInfo.td.

-Eli

Maybe I didn't describe the question very well.

I want to match these patterns:

  (and (mul node:$val0, node:$val1))
  (and (add node:$val0, node:$val1))
  (and (sub node:$val0, node:$val1))
  (and (udiv node:$val0, node:$val1))

into "four" different machines instructions, respectively:

  MUL_AND
  ADD_AND
  SUB_AND
  UDIV_AND

That is, this machine is capable of doing an arithmetic operation and a
"following" AND operation by a single machine instruction. There are a
lot
of arithmetic operations but they can only be combined with a following AND
operation. It's important that only the following AND can be merged/combined
with the arithmetic operation. The pattern:

   (mul node:$val0, (AND))

can _not_ be matched.

The problem is, it seems to me, that the instruction returned in these
patterns is always the AND, which is the "root" of these partial DAG
pattern, instead of the arithmetic operation. The LLVM instruction selector
is capable of doing this "look ahead" matching? What is the suggested
way to
do this?


PS: For GPU guys, I am trying to match the writemask operation after an
arithmetic operation.

  



Eli Friedman-2 wrote:
> 
> On Mon, Jan 5, 2009 at 2:32 PM, Alex <alex.lavoro.propio at
gmail.com> wrote:
>> In .td file, if the pattern to match the DAG is:
>>
>> (vector_shuffle (mul build_vector, build_vector))
>>
>> is it possible to return 'mul' (SDNode*) instead of returning
the first
>> 'vector_shuffle'?
>>
>> It seems to me that the default instruction selector can only return
the
>> 'root' node of the pattern.
> 
> The simplest thing to do is to map a vector_shuffle to another
> vector_shuffle; there shouldn't be any issues with that, I think.  Is
> there some reason you don't want to write it that way?
> 
> Note that you can use a custom PatFrag to match an instruction with a
> single use... see, for example, "and_su" in X86InstrInfo.td.
> 
> -Eli
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> 
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