search for: val0

...i.cpp index 41b91e8..e5b767f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) src0 = fetchSrc(0, c); val0 = getScratch(); mkOp1(OP_FLOOR, TYPE_F32, val0, src0); - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); } break; case TGSI_OPCODE_ROUND: -- 2.0.4

...--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) >> src0 = fetchSrc(0, c); >> val0 = getScratch(); >> mkOp1(OP_FLOOR, TYPE_F32, val0, src0); >> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); >> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); >> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); >> } >> break...

Maybe I didn't describe the question very well. I want to match these patterns: (and (mul node:$val0, node:$val1)) (and (add node:$val0, node:$val1)) (and (sub node:$val0, node:$val1)) (and (udiv node:$val0, node:$val1)) into "four" different machines instructions, respectively: MUL_AND ADD_AND SUB_AND UDIV_AND That is, this machine is capable of doing an arithmetic oper...

...codegen/nv50_ir_from_tgsi.cpp >>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >>>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) >>>> src0 = fetchSrc(0, c); >>>> val0 = getScratch(); >>>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0); >>>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); >>>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); >>>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); >&g...

...Type(), Indices.begin(), Indices.end())) @@ -2156,7 +2195,8 @@ ParseIndexList(Indices) || ParseToken(lltok::rparen, "expected ')' in insertvalue constantexpr")) return true; - if (!isa<StructType>(Val0->getType()) && !isa<ArrayType>(Val0- >getType())) + if (!isa<StructType>(Val0->getType()) && !isa<ArrayType>(Val0- >getType()) && + !isa<UnionType>(Val0->getType())) How about changing this to use Type::isAggregateType()...

..., > Indices.end())) > @@ -2156,7 +2195,8 @@ > ParseIndexList(Indices) || > ParseToken(lltok::rparen, "expected ')' in insertvalue > constantexpr")) > return true; > - if (!isa<StructType>(Val0->getType()) && > !isa<ArrayType>(Val0->getType())) > + if (!isa<StructType>(Val0->getType()) && > !isa<ArrayType>(Val0->getType()) && > + !isa<UnionType>(Val0->getType())) > > How about changing this to use T...

...67f 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp > @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) > src0 = fetchSrc(0, c); > val0 = getScratch(); > mkOp1(OP_FLOOR, TYPE_F32, val0, src0); > - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); > + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); > + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); > } > break; > case TGSI_OPC...

...m/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) >>> src0 = fetchSrc(0, c); >>> val0 = getScratch(); >>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0); >>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); >>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); >>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); >>> } &...

..., > Indices.end())) > @@ -2156,7 +2195,8 @@ > ParseIndexList(Indices) || > ParseToken(lltok::rparen, "expected ')' in insertvalue > constantexpr")) > return true; > - if (!isa<StructType>(Val0->getType()) && > !isa<ArrayType>(Val0->getType())) > + if (!isa<StructType>(Val0->getType()) && > !isa<ArrayType>(Val0->getType()) && > + !isa<UnionType>(Val0->getType())) > > How about changing this to use T...

...se TGSI_OPCODE_USHR: > @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) > FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) > mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c)); > break; > + case TGSI_OPCODE_POW: > + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0)); > + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) > + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); > + break; Can you use mkMov ? Pretty please :) -Emil > case TGSI_OPCODE_EX2: > case TGSI_OPCODE_L...

On Mon, Jan 5, 2009 at 2:32 PM, Alex <alex.lavoro.propio at gmail.com> wrote: > In .td file, if the pattern to match the DAG is: > > (vector_shuffle (mul build_vector, build_vector)) > > is it possible to return 'mul' (SDNode*) instead of returning the first > 'vector_shuffle'? > > It seems to me that the default instruction selector can only return

....va_start(i8**) declare void @llvm.va_end(i8**) define i64 @foo(...) { %va = alloca i8*, i32 16 ; 4 words should be enough? call void @llvm.va_start(i8** %va) %x = va_arg i8** %va, i64 call void @llvm.va_end(i8** %va) ret i64 %x } ;; should return 123 define i32 @main() { %val0 = call i64(...) @foo(i64 123) %res = trunc i64 %val0 to i32 ret i32 %res } Running this returns mostly 0, but sometimes 123. $ while sleep 1; do lli bug.ll; echo $?; done 123 0 0 0 123 0 0 Adding { alignstack=8 } to main makes it always return 123. Is this a bug or just a missing piece...

In .td file, if the pattern to match the DAG is: (vector_shuffle (mul build_vector, build_vector)) is it possible to return 'mul' (SDNode*) instead of returning the first 'vector_shuffle'? It seems to me that the default instruction selector can only return the 'root' node of the pattern. Alex. -------------- next part -------------- An HTML attachment was scrubbed...

...53,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) >>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) >>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c)); >>> break; >>> + case TGSI_OPCODE_POW: >>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0)); >>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) >>> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); >>> + break; >> Can you use mkMov ? Pretty please :) > > The two are used fair...

OK here's the patch for real this time :) On Fri, Jan 15, 2010 at 4:36 PM, Talin <viridia at gmail.com> wrote: > Here's a work in progress of the union patch. Note that the test "union.ll" > does not work, so you probably don't want to check this in as is. However, > I'd be interested in any feedback you're willing to give. > > -- > -- Talin

Here's a work in progress of the union patch. Note that the test "union.ll" does not work, so you probably don't want to check this in as is. However, I'd be interested in any feedback you're willing to give. -- -- Talin -------------- next part -------------- An HTML attachment was scrubbed... URL:

...If you mean at the IR level, then I think yes; since otherwise it is > legal to do transforms that break byte-wise atomicity in the IR, e.g.: > > i32* ptr = ... > i32 val = *ptr > > => // Since no threads can be legally racing on *ptr > > i32* ptr = ... > i32 val0 = *ptr > i32 val1 = *ptr > i32 val = (val0 & 1) | (val1 & ~1); > > > If you're talking about the hardware level, then I'm not sure; and my > guess is that the answer is almost certainly arch-dependent. I meant the case when we have a load by bytes pattern like...

...rnate version of >> another? > > There is not a way to represent --- instruction I1 is an alternative > for instruction I2 --- in LLVM IR. Could there be any interest in this functionality? Do you think bending the meaning of existing constructs like select i1 undef, <ty> <val0>, <ty> <val1> (for instructions) or switch i1 undef, label <bb0>, i1 1, label <bb1> (for basic blocks) could be feasible/acceptable?

Hi. This patchset is preparation patches for ia64/pv_ops support. They are almost trivial and mainly make kernel paravirtualization friendly. thanks, Diffstat: arch/ia64/kernel/irq_ia64.c | 1 - include/asm-ia64/intrinsics.h | 11 +++++++++++ include/asm-ia64/mmu_context.h | 6 +----- include/asm-ia64/smp.h | 2 ++ include/asm-ia64/system.h | 10 ++++++++-- 5 files

...case TGSI_OPCODE_ISHR: case TGSI_OPCODE_USHR: @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c)); break; + case TGSI_OPCODE_POW: + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0)); + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); + break; case TGSI_OPCODE_EX2: case TGSI_OPCODE_LG2: val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))-&...