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...implest thing to do is to map a vector_shuffle to another vector_shuffle; there shouldn't be any issues with that, I think. Is there some reason you don't want to write it that way? Note that you can use a custom PatFrag to match an instruction with a single use... see, for example, "and_su" in X86InstrInfo.td. -Eli

In .td file, if the pattern to match the DAG is: (vector_shuffle (mul build_vector, build_vector)) is it possible to return 'mul' (SDNode*) instead of returning the first 'vector_shuffle'? It seems to me that the default instruction selector can only return the 'root' node of the pattern. Alex. -------------- next part -------------- An HTML attachment was scrubbed...

I have been doing some playing with the patterns that define complex instructions, and I saw a behavior that doesn't look right. I think its a bug in the PPC backend. The 32-bit PPC .td file defines a pattern for the fnmsubs instruction like this: def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,

...map a vector_shuffle to another > vector_shuffle; there shouldn't be any issues with that, I think. Is > there some reason you don't want to write it that way? > > Note that you can use a custom PatFrag to match an instruction with a > single use... see, for example, "and_su" in X86InstrInfo.td. > > -Eli > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -- View this message in context: http://w...