llvm dev - Dec 2008 - [LLVMdev] Register Dependencies and Register Allocation

I'm writing a back-end for an architecture that supports multi-word loads.
As a concrete example, "ldqw r0, [addr]" would load a quadword (4
words)
into 4 registers starting with r0 (implicit writes to r1, r2, and r3).

First, is there any currently supported architecture that has anything like
this?  I suspect not.  If not, I hope someone might help me figure out how
to make this work, particularly with the cooperation of the register
allocator?  In particular, I need the register allocator to understand that
there are multiple, contiguous register assignments, and that their
locations are moreover dependent on the specified initial input register.

I thought about defining a set of special register classes to group
contiguous registers for each load size (2, 4, and 8), but this doesn't feel
very satisfying.  Is this the right approach?  I'm wondering if it would
work, and if so, if it would also still be efficient.

Marc
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On Dec 23, 2008, at 11:03 AMPST, Marc de Kruijf wrote:
>
> I'm writing a back-end for an architecture that supports multi-word  
> loads.  As a concrete example, "ldqw r0, [addr]" would load a  
> quadword (4 words) into 4 registers starting with r0 (implicit  
> writes to r1, r2, and r3).
ARM has this.  It currently works by creating such instructions in a  
peephole pass following register allocation, which is not ideal.
I think defining a quad-word register class containing 4 smaller  
registers should be doable.  See the handling of floating point on  
Sparc.
> First, is there any currently supported architecture that has  
> anything like this?  I suspect not.  If not, I hope someone might  
> help me figure out how to make this work, particularly with the  
> cooperation of the register allocator?  In particular, I need the  
> register allocator to understand that there are multiple, contiguous  
> register assignments, and that their locations are moreover  
> dependent on the specified initial input register.
>
> I thought about defining a set of special register classes to group  
> contiguous registers for each load size (2, 4, and 8), but this  
> doesn't feel very satisfying.  Is this the right approach?  I'm  
> wondering if it would work, and if so, if it would also still be  
> efficient.
>
> Marc
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

On Dec 23, 2008, at 11:03 AM, Marc de Kruijf wrote:
>
> I'm writing a back-end for an architecture that supports multi-word  
> loads.  As a concrete example, "ldqw r0, [addr]" would load a  
> quadword (4 words) into 4 registers starting with r0 (implicit  
> writes to r1, r2, and r3).
>
> First, is there any currently supported architecture that has  
> anything like this?  I suspect not.  If not, I hope someone might  
> help me figure out how to make this work, particularly with the  
> cooperation of the register allocator?  In particular, I need the  
> register allocator to understand that there are multiple, contiguous  
> register assignments, and that their locations are moreover  
> dependent on the specified initial input register.
>
> I thought about defining a set of special register classes to group  
> contiguous registers for each load size (2, 4, and 8), but this  
> doesn't feel very satisfying.  Is this the right approach?  I'm  
> wondering if it would work, and if so, if it would also still be  
> efficient.
Probably the best way to handle this is with subregs.  Just define a  
register file with these "super registers" and say that they alias the
4 individual registers.  This is how the sparc backend handles its FP  
register file (where one double reg is 2 float regs).

-Chris

Okay, this is what I suspected.  You guys are awesome.  Thanks for
confirming.

On Tue, Dec 23, 2008 at 1:17 PM, Dale Johannesen <dalej at apple.com>
wrote:
>
> On Dec 23, 2008, at 11:03 AMPST, Marc de Kruijf wrote:
>
> >
> > I'm writing a back-end for an architecture that supports
multi-word
> > loads.  As a concrete example, "ldqw r0, [addr]" would load
a
> > quadword (4 words) into 4 registers starting with r0 (implicit
> > writes to r1, r2, and r3).
>
> ARM has this.  It currently works by creating such instructions in a
> peephole pass following register allocation, which is not ideal.
> I think defining a quad-word register class containing 4 smaller
> registers should be doable.  See the handling of floating point on
> Sparc.
>
> > First, is there any currently supported architecture that has
> > anything like this?  I suspect not.  If not, I hope someone might
> > help me figure out how to make this work, particularly with the
> > cooperation of the register allocator?  In particular, I need the
> > register allocator to understand that there are multiple, contiguous
> > register assignments, and that their locations are moreover
> > dependent on the specified initial input register.
> >
> > I thought about defining a set of special register classes to group
> > contiguous registers for each load size (2, 4, and 8), but this
> > doesn't feel very satisfying.  Is this the right approach? 
I'm
> > wondering if it would work, and if so, if it would also still be
> > efficient.
> >
> > Marc
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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