Displaying 2 results from an estimated 2 matches for "45897c5c".
2008 Dec 23
0
[LLVMdev] Register Dependencies and Register Allocation
On Dec 23, 2008, at 11:03 AMPST, Marc de Kruijf wrote:
>
> I'm writing a back-end for an architecture that supports multi-word
> loads. As a concrete example, "ldqw r0, [addr]" would load a
> quadword (4 words) into 4 registers starting with r0 (implicit
> writes to r1, r2, and r3).
ARM has this. It currently works by creating such instructions in a
2008 Dec 23
3
[LLVMdev] Register Dependencies and Register Allocation
I'm writing a back-end for an architecture that supports multi-word loads.
As a concrete example, "ldqw r0, [addr]" would load a quadword (4 words)
into 4 registers starting with r0 (implicit writes to r1, r2, and r3).
First, is there any currently supported architecture that has anything like
this? I suspect not. If not, I hope someone might help me figure out how
to make this