similar to: [LLVMdev] Register Dependencies and Register Allocation

On Dec 23, 2008, at 11:03 AMPST, Marc de Kruijf wrote: > > I'm writing a back-end for an architecture that supports multi-word > loads. As a concrete example, "ldqw r0, [addr]" would load a > quadword (4 words) into 4 registers starting with r0 (implicit > writes to r1, r2, and r3). ARM has this. It currently works by creating such instructions in a

On Jan 9, 2009, at 11:37 AMPST, Evan Cheng wrote: > This looks like a bar in ARMInstrInfo.td: > > BX_RET should be marked with Uses = [LR] since it uses LR. However, > this won't work if there is a call BL before the BX_RET. BL is marked > as if it implicitly define LR. So we'll end up with this (hello world > example): PPC has the call (BL) marked with Defs=LR and the

Hi, I have a question about implementing subword register allocation problems (see the REFERENCES in the end of this message) on LLVM. I have algorithms, but don't know the best way to implement them in LLVM. I asked similar question before: http://lists.cs.uiuc.edu/pipermail/llvmdev/2005- May/004001.html Because I still don't have a satisfying solution now, I try to elaborate it

On Feb 23, 2009, at 10:30 AMPST, Aaron Gray wrote: > On Mon, Feb 23, 2009 at 6:22 PM, Aaron Gray <aaronngray.lists at googlemail.com > > wrote: > On Mon, Feb 23, 2009 at 6:09 PM, Dale Johannesen <dalej at apple.com> > wrote: > These benchmarks are not distributed with llvm (which doesn't have the > legal right to distribute Spec, for example). If you have

On Mon, Feb 23, 2009 at 6:09 PM, Dale Johannesen <dalej at apple.com> wrote: > These benchmarks are not distributed with llvm (which doesn't have the > legal right to distribute Spec, for example). If you have them from > another source, you need to configure --with-externals=<path> Okay, thanks. Thre should be better warning/error reporting though. Aaron > >

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

On Mon, Feb 23, 2009 at 6:22 PM, Aaron Gray <aaronngray.lists at googlemail.com > wrote: > On Mon, Feb 23, 2009 at 6:09 PM, Dale Johannesen <dalej at apple.com> wrote: > >> These benchmarks are not distributed with llvm (which doesn't have the >> legal right to distribute Spec, for example). If you have them from >> another source, you need to configure

Hello LLVM Community (specifically anyone working with ARM Cortex-M), While trying to compile the Newlib C library I found that Clang10 was generating slightly larger binaries than the libc from the prebuilt gcc-arm-none-eabi toolchain. I looked at a few specific functions (memcpy, strcpy, etc.) and noticed that LLVM does not tend to generate load/store instructions with a register offset (e.g.

Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that

This looks like a bar in ARMInstrInfo.td: BX_RET should be marked with Uses = [LR] since it uses LR. However, this won't work if there is a call BL before the BX_RET. BL is marked as if it implicitly define LR. So we'll end up with this (hello world example): Live Ins: %LR %R7 %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 STR %LR<kill>, %SP,

Hi, I am getting this when running make-test :- $ /usr/src/llvm-test-2.5/configure checking for spec95 benchmark sources... no, not found in /home/vadve/shared/ben chmarks/spec95/benchspec checking for spec2000 benchmark sources... no, not found in /home/vadve/shared/b enchmarks/speccpu2000/benchspec checking for spec2006 benchmark sources... no, not found in /home/vadve/shared/b

Hi Evan, Thanks for your feedback! 2009/1/7 Evan Cheng <evan.cheng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand,

I've been playing around with the new IndirectBr and BlockAddress types. I'm finding that in CodeGen, during "EliminateMostlyEmptyBlocks", BlockAddresses are not updated to point to the newly merged block if the original block was eliminated. This is causing me problems. Mind you, I'm experimenting with this using the Sparc backend, which could be the source of blame, but

Hi all, The remaining issue to be decided for the OggPCM2 spec is the support of chunked vs interleaved data. Just so that everyone understands what we are talking about, consider a stereo file that gets stored as an OggPCM file. Within an OggPCM packet, the audio samples for the left and right channels can be stored as interleaved where the samples would be: l0, r0, l1, r1, ..... lN, rN

These benchmarks are not distributed with llvm (which doesn't have the legal right to distribute Spec, for example). If you have them from another source, you need to configure --with-externals=<path> On Feb 23, 2009, at 10:02 AMPST, Aaron Gray wrote: > Hi, > > I am getting this when running make-test :- > > $ /usr/src/llvm-test-2.5/configure > checking for

Dale Johannesen wrote: > On Feb 23, 2009, at 10:30 AMPST, Aaron Gray wrote: > > On Mon, Feb 23, 2009 at 6:22 PM, Aaron Gray <aaronngray.lists at googlemail.com<mailto:aaronngray.lists at googlemail.com>> wrote: > On Mon, Feb 23, 2009 at 6:09 PM, Dale Johannesen <dalej at apple.com<mailto:dalej at apple.com>> wrote: > These benchmarks are not distributed with

My apologies. This problem was indeed with my changes to the backend. Next time I will more carefully examine the source of the problem. :) On Fri, Feb 26, 2010 at 12:40 PM, Marc de Kruijf <dekruijf at wisc.edu> wrote: > I've been playing around with the new IndirectBr and BlockAddress types. > I'm finding that in CodeGen, during "EliminateMostlyEmptyBlocks", >

Hello Everyone, I am trying to make a new LLVM backend target for Intel GPU. I would start from targeting OpenCL language first. But I am not quite familiar with LLVM backend infrastructure. I have some problem on describing the RegisterInfo. Intel GPU launches lots of hardware threads to do GPGPU workload. Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte. Each

The LLVA and LLVM papers motivate the GetElementPtr instruction by arguing that it abstracts implementation details, in particular pointer size, from the compiler. While it does this fine for pointer addresses, it does not manage it for address offsets. Consider the following code: $ cat test.c int main() { int *x[2]; int **y = &x[1]; return (y - x); } $ llvm-gcc -O3 -c test.c

Yes, I'm not arguing that there is a dependence, just that it's not a clobber dependence. The case of a load is already considered earlier in that function and with isLoad == false it returns MemDepResult::getDef(). My question is: why should a read-only call (which yields AliasAnalysis::Ref and is handled in this code fragment) be any different from e.g. a load. Isn't a read-only