llvm dev - Sep 2007 - [LLVMdev] New to LLVM, Help needed

Hi,

I have started to write an llvm backend for one of our microcontrollers
(PICxx). I started studying the framework of PowerPc backend of llvm and
decided to start by following that framework. Now I have most of the
classes and Tblgen files written for a very basic hypothetical
microcontroller with very few instructions.

The project builds and the llc recognizes the new processor, however,
when it reaches the point where it wants to lower llvm IR to PICxx DAG,
it asserts in LegalizeDAG.cpp in ExpandOp() function after it hits the
default case of switch(Node->getOpcode())

Can someone please help me understand how am I ending up in the default
case?

 

Thanks,

A.

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070907/1b948f34/attachment.html>

On Sep 7, 2007, at 4:50 PM, <Alireza.Moshtaghi at microchip.com>  
<Alireza.Moshtaghi at microchip.com> wrote:
> I have started to write an llvm backend for one of our  
> microcontrollers (PICxx). I started studying the framework of  
> PowerPc backend of llvm and decided to start by following that  
> framework. Now I have most of the classes and Tblgen files written  
> for a very basic hypothetical microcontroller with very few  
> instructions.
Cool!
> The project builds and the llc recognizes the new processor,  
> however, when it reaches the point where it wants to lower llvm IR  
> to PICxx DAG, it asserts in LegalizeDAG.cpp in ExpandOp() function  
> after it hits the default case of switch(Node->getOpcode())
>
> Can someone please help me understand how am I ending up in the  
> default case?
It's hard to say. You'd have to look at what the Node->getOpcode()  
is. It should be one of the ones that's being handled. It's not, so  
you need to figure out why it isn't, where it's coming from, and how  
to get it to be one of the opcodes handled. Check your  
PICxxISelLowering.cpp (?) file and see what it's doing with that  
opcode. Are you really going to "expand" it, or should it do  
something else (legal, promote)?

These are a few tips. Others will jump in with better ideas, I'm sure.

-bw

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070908/cddeef29/attachment.html>

On Sep 7, 2007, at 4:50 PM, <Alireza.Moshtaghi at microchip.com>  
<Alireza.Moshtaghi at microchip.com> wrote:
> Hi,
>
> I have started to write an llvm backend for one of our  
> microcontrollers (PICxx).
Is the documentation for the PICxx series you're writing this for  
publicly available? Is it planned to contribute the back end to the  
public LLVM project? I suspect there are people out there who would  
help with the back end if the source were in the public LLVM repo.

--
Christopher Lamb



-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070908/b6c2d30d/attachment.html>

Please do a debug build and run it under gdb. Let us know where it is  
asserting and what it is asserting on so we can help you.

Evan

On Sep 7, 2007, at 4:50 PM, Alireza.Moshtaghi at microchip.com wrote:
> Hi,
> I have started to write an llvm backend for one of our  
> microcontrollers (PICxx). I started studying the framework of  
> PowerPc backend of llvm and decided to start by following that  
> framework. Now I have most of the classes and Tblgen files written  
> for a very basic hypothetical microcontroller with very few  
> instructions.
> The project builds and the llc recognizes the new processor,  
> however, when it reaches the point where it wants to lower llvm IR  
> to PICxx DAG, it asserts in LegalizeDAG.cpp in ExpandOp() function  
> after it hits the default case of switch(Node->getOpcode())
> Can someone please help me understand how am I ending up in the  
> default case?
>
> Thanks,
> A.
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070910/3982b929/attachment.html>

More information on this... still not working

When I build the project for Debug and run the program, the following
message is printed before assert.

NODE: 0x937bac8:  i64 = GlobalAddress <i32* @var> 0

I guess it is expecting that GlobalAddress be legalized before reaching
ExpandOp(). I haven't implemented anything for ISD::GlobalAddress, and
that may explain it, however, I couldn't find much about it in the
PowerPC implementation either. The only thing is in the ctor of
PPCTargetLowering there is setOperationAction(ISD::GlobalAddress,
MVT::i32, Custom);  and 

setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);

 

so I also added these two function calls to my ctor of
PICxxTargetLowering. Nothing changed. I also tried "Expand" and
"Legal"
instead of "Custom", still no progress. I'm sure I am missing some
thing
here.

 

Any idea??

 

Thanks

A.

________________________________

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Evan Cheng
Sent: Monday, September 10, 2007 10:29 AM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] New to LLVM, Help needed

 

Please do a debug build and run it under gdb. Let us know where it is
asserting and what it is asserting on so we can help you.

 

Evan

 

On Sep 7, 2007, at 4:50 PM, Alireza.Moshtaghi at microchip.com wrote:





Hi,

I have started to write an llvm backend for one of our microcontrollers
(PICxx). I started studying the framework of PowerPc backend of llvm and
decided to start by following that framework. Now I have most of the
classes and Tblgen files written for a very basic hypothetical
microcontroller with very few instructions.

The project builds and the llc recognizes the new processor, however,
when it reaches the point where it wants to lower llvm IR to PICxx DAG,
it asserts in LegalizeDAG.cpp in ExpandOp() function after it hits the
default case of switch(Node->getOpcode())

Can someone please help me understand how am I ending up in the default
case?

 

Thanks,

A.

_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

 

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20070911/705e8e94/attachment.html>