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Hello, The current code in PPCTargetLowering::LowerFormalArguments_SVR4 contains a FIXME over the code which saves the live floating-point registers to the stack. The FIXME states that this should only be done if CR bit 6 is set. I've been told that the lack of this check is preventing clang/LLVM from compiling a functional FreeBSD kernel...

I hate to be bothersome, but can someone please comment on this? Thanks again, Hal On Thu, 3 May 2012 14:49:04 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > Hello, > > The current code in PPCTargetLowering::LowerFormalArguments_SVR4 > contains a FIXME over the code which saves the live floating-point > registers to the stack. The FIXME states that this should only be done > if CR bit 6 is set. I've been told that the lack of this check is > preventing clang/LLVM from compiling a funct...

...e to be bothersome, but can someone please comment on this? > > > > Thanks again, > > Hal > > > > On Thu, 3 May 2012 14:49:04 -0500 > > Hal Finkel <hfinkel at anl.gov> wrote: > > > >> Hello, > >> > >> The current code in PPCTargetLowering::LowerFormalArguments_SVR4 > >> contains a FIXME over the code which saves the live floating-point > >> registers to the stack. The FIXME states that this should only be > >> done if CR bit 6 is set. I've been told that the lack of this > >> check is preventi...

...nkel <hfinkel at anl.gov> wrote: > I hate to be bothersome, but can someone please comment on this? > > Thanks again, > Hal > > On Thu, 3 May 2012 14:49:04 -0500 > Hal Finkel <hfinkel at anl.gov> wrote: > >> Hello, >> >> The current code in PPCTargetLowering::LowerFormalArguments_SVR4 >> contains a FIXME over the code which saves the live floating-point >> registers to the stack. The FIXME states that this should only be done >> if CR bit 6 is set. I've been told that the lack of this check is >> preventing clang/LLVM from c...

...meone please comment on this? >>> >>> Thanks again, >>> Hal >>> >>> On Thu, 3 May 2012 14:49:04 -0500 >>> Hal Finkel <hfinkel at anl.gov> wrote: >>> >>>> Hello, >>>> >>>> The current code in PPCTargetLowering::LowerFormalArguments_SVR4 >>>> contains a FIXME over the code which saves the live floating-point >>>> registers to the stack. The FIXME states that this should only be >>>> done if CR bit 6 is set. I've been told that the lack of this >>>> check...

...Why is this taking two arguments? I don't think "getValue(I.getArgOperand(1))" should be there. > return 0; > } > case Intrinsic::gcroot: > --- a/lib/Target/PowerPC/PPCISelLowering.cpp > +++ b/lib/Target/PowerPC/PPCISelLowering.cpp > @@ -211,6 +211,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) > setOperationAction(ISD::TRAP, MVT::Other, Legal); > > // TRAMPOLINE is custom lowered. > + setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); > + setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); > &gt...

...pr 22, 2008 at 12:30 AM, Evan Cheng <evan.cheng at apple.com> wrote: > More nitpicks: > ... > No need for else here. :-) Done > SPDiff = (int)CallerMinReservedArea - (int)ParamSize; > > Just change last statement to > int SPDiff = (int)... Done > > +bool > +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, > + SDOperand Ret, > + SelectionDAG& > DAG) const { > + // Variable argument functions > + // are not supported. >...

Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc:

...e. :-) + int SPDiff = 0; + + PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); + unsigned CallerMinReservedArea = FI->getMinReservedArea(); + SPDiff = (int)CallerMinReservedArea - (int)ParamSize; Just change last statement to int SPDiff = (int)... +bool +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, + SDOperand Ret, + SelectionDAG& DAG) const { + // Variable argument functions + // are not supported. Why two separate lines? + if (...

Hi Nemanja, I'm attaching a patch that builds on D54583 and implements what we discussed on IRC earlier today. Particularly: * Make LowerCallTo() a virtual function, so it can be wrapped by a subclass. * Implement LowerCallTo() in PPCTargetLowering to wrap TargetLowering::LowerCallTo() and legalize the return node when targeting SPE. * Augment PPCTargetLowering::LowerCall_32SVR4() to legalize MVT::f64 arguments that have been pre-processed into EXTRACT_ELEMENT(i64 BITCAST f64, 0/1) The purpose of this being to legalize intermediate i...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote: > >> The...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can...

...at apple.com> > wrote: >> More nitpicks: >> ... >> No need for else here. :-) > Done >> SPDiff = (int)CallerMinReservedArea - (int)ParamSize; >> >> Just change last statement to >> int SPDiff = (int)... > Done >> >> +bool >> +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, >> + SDOperand Ret, >> + SelectionDAG& >> DAG) const { >> + // Variable argument functions >> + // are not s...

Ah, didn't see that, that's what comes of trying to do something at 5pm :) I attached an updated patch which creates a virtual register instead of using R0. How does this look? Cheers, Gary Dan Gohman wrote: > PPCTargetLowering::EmitInstrWithCustomInserter has a reference > to the current MachineFunction for other purposes. Can you use > MachineFunction::getRegInfo instead? > > Dan > > On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > > Would it be acceptable to change MachineInstr::getRegInfo &gt...

...() #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at ValueTypes.h:317 #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\ 5 #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) at PPCISelLowering.cpp:3200 #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) at PPCISelLowering.cpp:3766 #9 0x0051bed6 in (anony...

...A better solution would be to fix the lowering to > produce two instructions instead of this pseudo instruction. Hi Chris, I'd prefer to fix the lowering if possible; the pseudo instructions are only used in three places, so it shouldn't be a huge change. I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP however: how do I do that? FWIW the code it needs to emit is: ; inputs: ptr, oldval, newval loop: lwarx $tmp, 0, $ptr cmpw $oldval, $tmp bne- exit stwcx. $newval, 0, $ptr bne- loop exit: ... Cheers, Gary -- http://gben...

...this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See PPCTargetLowering::EmitInstrWithCustomInserter(). Evan On Jun 30, 2008, at 6:10 AM, Gary Benson wrote: > Chris Lattner wrote: >> On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: >>> def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: >>> $label), >>>...

....cwru.edu<mailto:jrh29 at alumni.cwru.edu>> wrote: Hi Nemanja, I'm attaching a patch that builds on D54583 and implements what we discussed on IRC earlier today. Particularly: * Make LowerCallTo() a virtual function, so it can be wrapped by a subclass. * Implement LowerCallTo() in PPCTargetLowering to wrap TargetLowering::LowerCallTo() and legalize the return node when targeting SPE. * Augment PPCTargetLowering::LowerCall_32SVR4() to legalize MVT::f64 arguments that have been pre-processed into EXTRACT_ELEMENT(i64 BITCAST f64, 0/1) The purpose of this being to legalize intermediate i...

...::getVectorElementType (this=0xbfffdda4) > at ValueTypes.h:317 > #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, > SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, > dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\ > 5 > #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR > (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) > at PPCISelLowering.cpp:3200 > #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation > (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) > at PPCISelLowering.cpp:3766...