llvm dev - Mar 2007 - [LLVMdev] ISel using an operand as both source and destination

I have some instructions that use a register as both an input and as  
the output. Is there a way to specify this constraint in the  
InstrInfo.td or will this have to be custom selected/lowered?

Thanks
--
Christopher Lamb
christopher.lamb at gmail.com


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I see in the x86 InstInfo.td the following for the INC instructions:

def INC8r  : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b}
$dst",
                [(set GR8:$dst, (add GR8:$src, 1))]>;

Which seem to have the same restriction that I'm trying to implement,  
but I don't understand how this ensures that $src and $dst are the  
same register.

--
Christopher Lamb
christopher.lamb at gmail.com


On Mar 1, 2007, at 12:03 PM, Christopher Lamb wrote:
> I have some instructions that use a register as both an input and  
> as the output. Is there a way to specify this constraint in the  
> InstrInfo.td or will this have to be custom selected/lowered?
>
> Thanks
> --
> Christopher Lamb
> christopher.lamb at gmail.com
>
>

On Thu, 1 Mar 2007, Christopher Lamb wrote:
> I see in the x86 InstInfo.td the following for the INC instructions:
>
> def INC8r  : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b}
$dst",
>                [(set GR8:$dst, (add GR8:$src, 1))]>;
>
> Which seem to have the same restriction that I'm trying to implement,
> but I don't understand how this ensures that $src and $dst are the
> same register.
The trick is that it's nested in this block:

let isTwoAddress = 1 in {
...

Marking an instruction 'two address' tells the codegen that the first
two
registers must be constrained to be the same physreg.  There is a more 
general mechanism wih constraints you can also use.

-Chris

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