search for: mrm0r

...: BinOpRM_F<0x84, "test", Xi16, X86testpat>; def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>; def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>; def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>; def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; def TEST8mi : BinOpMI_F&l...

I have a question: In the pattern below from X86 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\tdst", [(set GR8:$dst, (add GR8:$src, 1))]>; Since we are emitting only "inc $dst", What makes sure that the $src and $dst are same register? - Sanjiv

sanjiv gupta wrote: > I have a question: > In the pattern below from X86 > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > "inc{b}\tdst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Since we are emitting only "inc $dst", > What makes sure that the $src and $dst are same register? > > - Sanjiv It's enclosed inside : let isTwoAd...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Tue, 2008-09-23 at 13:33 +0100, Richard Osborne wrote: > sanjiv gupta wrote: > > I have a question: > > In the pattern below from X86 > > > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > > "inc{b}\tdst", > > [(set GR8:$dst, (add GR8:$src, 1))]>; > > > > Since we are emitting only "inc $dst", > > What makes sure that the $src and $dst are same register? > > > > - Sanjiv >...

I have some instructions that use a register as both an input and as the output. Is there a way to specify this constraint in the InstrInfo.td or will this have to be custom selected/lowered? Thanks -- Christopher Lamb christopher.lamb at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL:

I see in the x86 InstInfo.td the following for the INC instructions: def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; Which seem to have the same restriction that I'm trying to implement, but I don't understand how this ensures that $src and $dst are the same register. -- Christopher Lamb ch...

On Thu, 1 Mar 2007, Christopher Lamb wrote: > I see in the x86 InstInfo.td the following for the INC instructions: > > def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Which seem to have the same restriction that I'm trying to implement, > but I don't understand how this ensures that $src and $dst are the > same register. The...

...s of the form: Error: Primary decode conflict: TEST64ri32 would overwrite CACHE_OPERAND_B64i ModRM 199 Opcode 247 Context IC_64BIT_REXW When I look at the definition of TEST64ri32, I see: let Predicates = [In64BitMode] in def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; It looks like TEST64ri32 is using opcode 0xF6 -- why is there a conflict with 0xF1? Even if I comment out TEST64ri32 (which I recognize is not a good idea), I still get a similar error: Error: Primary decode conflict: NOT64r would overwrite CACHE_OPERAND_B64i ModRM 215 Opcode 247 Context...

hi, i am struggling to understand how MRMDestReg is used in X86. in X86InstrFormat.td, we have this: class Format<bits<7> val> { bits<7> Value = val; } def MRMDestReg : Format<3> i think eventually, MRMDestReg is mapped back to ModMRM byte. but this still doesnt make sense to me why MRMDestReg is defined this way, and how it is mapped back to ModRM byte. any hint

I found that LLVM were using Binutils to assemble the Assembly Code to the Machine Code, so I have a question, why LLVM don't direct generate the machine code? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080923/b7e42591/attachment.html>

On Sep 22, 2008, at 13:36, 罗勇刚 wrote: > I found that LLVM were using Binutils to assemble the Assembly Code > to the Machine Code, so I have a question, why LLVM don't direct > generate the machine code? There was a protracted and rather uninteresting discussion of this matter on this list some months ago. I'll summarize the outcome of that thread briefly: LLVM does

sanjiv gupta wrote: > On Tue, 2008-09-23 at 13:33 +0100, Richard Osborne wrote: > >> sanjiv gupta wrote: >> >>> I have a question: >>> In the pattern below from X86 >>> >>> def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), >>> "inc{b}\tdst", >>> [(set GR8:$dst, (add GR8:$src, 1))]>; >>> >>> Since we are emitting only "inc $dst", >>> What makes sure that the $src and $dst are same register? >>> >&...

Hi, Is it possible to define an Instruction with tablegen that reads and writes the same register? For example, an increment instruction that reads a value from a register, adds one to it and then writes the result back to the same register. Thanks, Tom

...lowing two instructions are used to adjust the stack pointer +// in the case where the callee has more arguments than the caller +// an area is created where the return addr can be safely moved to +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def TCADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32: $src1, i32imm:$src2), + "add{l}\t{$src2, $dst|$dst, $src2}", + []>; +} + +def TCSUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32: $src1, i32imm:$src2), + "sub{l}\t{$src2, $dst|$dst,...

...swapped. Rarely used MRMSrcRegOp4 - like MRMSrcReg, but a second source register is encoded in bits [7:4] of an immediate. modrm[2:0] encodes the 4th operand. Rarely used MRMXr - modrm.mod==0x3, with a value of 0 in modrm[5:3]. modrm[2:0] encodes a register. This is almost the same as MRM0r, but the disassembler ignores modrm[5:3] MRM0r-MRM7r - modrm.mod==0x3, with a fixed value(0-7) in modrm[5:3]. modrm[2:0] encode a register MRMC0-MRM_FF - Instruction encodes with a fixed value in the range 0xC0-0xFF in the modrm byte. e.g. VMCALL, MONITOR. No known instructions use a fixed v...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

...used to adjust the stack > pointer > +// in the case where the callee has more arguments than the caller > +// an area is created where the return addr can be safely moved to > +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. > +def TCADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32: > $src1, i32imm:$src2), > + "add{l}\t{$src2, $dst|$dst, $src2}", > + []>; > +} > + > +def TCSUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32: > $src1, i32imm:$src2), > +...

...86II::MRMSrcMem: { > + > + ++FinalSize; > + FinalSize += sizeMemModRMByte(MI, CurOp+1, IsPIC, Is64BitMode); > + CurOp += 5; > + if (CurOp != NumOps) > + FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); > + break; > + } > + > + case X86II::MRM0r: case X86II::MRM1r: > + case X86II::MRM2r: case X86II::MRM3r: > + case X86II::MRM4r: case X86II::MRM5r: > + case X86II::MRM6r: case X86II::MRM7r: > + ++FinalSize; > + FinalSize += sizeRegModRMByte(); > + > + if (CurOp != NumOps) { > + const MachineOperand &a...